最全的各类Flash比较讲解含时序

1、精选优质文档-倾情为你奉上1 Flash分类根据接口类型和操作时序的不同，主要讨论以下三种Flash。各种Flash支持的功能及工作特点简要如下列出： Normal Flash page(cache) read/programrandom data input/outputblock eraseMult_plane operation ToggleToggle mode interfacedata transfer at the rising and falling edge of DQSrandom data input/outputblock eraseinterleaved operat

2、ion ONFIONFI interfacesource synchronous/asynchronous data interfacetiming mode 0,1,2,3,4,5page(cache) read/programpausing data transfer random data input/outputblock eraseinterleaved operation 2 Flash memory organization块结构是Flash存储空间的基本组成单元，块也是擦除操作的最小单位，不能进行页擦除。块由许多Page组成，page是Flash编程和读操作的最小寻址单元。Fl

3、ash读写都是基于page的操作。Page由多个字节或字组成。 3 Flash functional block diagram Normal Toggle ONFI 4 Address map Normal不同容量的Hynix Flash的地址有效位数不一样，使用前阅具体产品资料地址说明。HY27UG084G2M Address MapIO0IO1IO2IO3IO4IO5IO6IO71st cycleA0A1A2A3A4A5A6A72nd cycleA8A9A10A11LLLL3rd cycleA12A13A14A15A16A17A18A194th cycleA20A21A22A23A24A

4、25A26A275th cycleA28A29LLLLLL其中：L must set to be “Low” Toggle同Hynix Flash一样，不同容量的Flash的地址有效位数不一样，使用前阅具体产品资料地址说明。K9PFGD8X5M Address MapIO0IO1IO2IO3IO4IO5IO6IO71st cycleA0A1A2A3A4A5A6A72nd cycleA8A9A10A11A12A13LL3rd cycleA14A15A16A17A18A19A20A214th cycleA22A23A24A25A26A27A28A295th cycleA30A31A32A33A34

5、LLLRow address：3 cycle，column address：2 cycle Column address: 12 cycle addressRow address:35 cycle address其中Page address：A14A20Plane address：A21Block address：A22A33*L must be set to “Low” ONFI Row address ： 3 cycles Column address： 2 cyclesRow address分三部分：LUN address，block address，page addressLUN ad

6、dressBlock addressPage address5 Timing Diagrams5.1 command latchNormal/Toggle/ONFI asynCLE=1 ALE=0 WE ONFI synCLE=1 ALE=0 W/R=1 CLK DQS don't care5.2 Address latch与地址锁存时序几乎相同，只是ALE，CLE的组合状态有区别。Command latch 中CLE有效，ALE无效。Address latch中CLE无效，ALE有效。Normal/Toggle/ONFI（asyn）CLE=0 ALE=1 WEONFI(syn)CLE

7、=0 ALE=1 W/R=1 CLK5.3 Data inputNormal/ONFI(asyn)CLE，ALE=0 WEToggleCLE，ALE=0 WE，RE=1， DQS ONFI(syn)CLE=1 ALE=1 （CLK） DQS 注：发送有些命令时发送或回复的数据需要repeated bytes传输。接收端（host or device）只锁存其中一字节，数据格式为D0D0D1D1D2D2，命令有：Set feature，Read ID，Read status and Read status enhanced。Data input（clk stopped） ALE，CLE Don&

8、#39;t care意义：停止时钟，降低功耗。当CLK置高时，数据写入data register，当R/B拉低时，数据存入Flash array。5.4 Data outputNormal/ONFI(asyn)ALE=0 CLE=0 WE=1 RE Toggle ALE=0 CLE=0 WE=1 RE DQS ONFI(syn) CLE=1 ALE=1 W/R=0 CLK DQS 6 Device operation page readNormal/Toggle/ONFI(asyn,syn)00h address cycles30h1 page data to the data registe

9、rs(RB#=0)70hread status 00h read data to I/O bus page programNormal/Toggle/ONFI(asyn,syn)80h address cycles1 page data to the data register10h R/B# = 0 70h, Read status Page cache program 80h5 address cyclesdata 15h 80haddress cycle 15h.80h5 address cycle 10h（all datas into flash cell，R/B# = 0 ） 70h

10、, read status I/O successful or fail NormalONFI异步时序同上，同步接口时，数据采用DDR传输Toggle(Not often used)Page cache read cache操作分两步，start cache read，end cache read ONFI:3Fh Normal:34h)31h data register to the cache register, next sequential page data from array to the data register（R/B# = 0） 3Fh the last page of

11、data from the data register to the cache register Normal/ONFI（asyn） Start Sequential(31h) Random(00h-31h) End ONFI（syn）略Toggle（not often used）random data inNormal/Toggle/ONFIrandom data outNormal/Toggle/ONFIblock erase(60h-D0h)Normal/Toggle/ONFIInterleaved operation interleaved page program ToggleONFI interleaved page readToggle将两plane数据下载至各自data register。再检测Chip1#，Chip#的状态，然后发命令由column address开始从Data Register读数据。Interleaved page read只适用于用interleaved page program编程的块。ONFI在输出数据前应先执行change read column enhanced 操作，确认先出数据的地址，否则输出的数据将是不确定的。 （发送读命令） （读数据输出）Interl