用VHDL语言设计555压控振荡器测频率参考模板

1、实验五 利用压控振荡器测量电压一、实验目的（1）以555定时器为基础设计压控振荡器（2）设计一个具有如下功能的简易频率计。 1. 可以测量压控振荡器产生的频率，用4位数码管显示 2.测量结果直接用十进制数值显示 3. 被测信号是压控振荡器产生的方波脉冲信号，根据设计的压控振荡器确定电压值 4. 具有超量程警告（可以用 LED 灯显示）二、实验设备与器材（1）计算机：Quartus 16.0软件；（2）硬件：Cyclone DE0-CV FPGA开发平台、555定时器、电阻、电容、可变电阻三、利用Multisim搭建仿真电路四、实验程序library ieee;use ieee.std_logi

2、c_1164.all;use ieee.std_logic_unsigned.all;- 计数器entity cnt10 is1 / 9 port (rst,fx,ena:in std_logic; cout: out std_logic; outy :out std_logic_vector(3 downto 0);end cnt10;architecture behv of cnt10 isbegin process (rst,ena,fx) - 定义变量 - <=是对信号赋值；而:=是对变量进行赋值 variable cqi :std_logic_vector(3 downto 0

3、); begin - others =>'0'是对数组cqi所有元素赋值0 if rst='1' then cqi :=(others =>'0'); elsif fx'event and fx='1' then if ena ='1' then if cqi < 9 then cqi:=cqi+1;cout<='0' elsif cqi=9 then cqi :=(others =>'0'); cout<='1' end

4、if; elsif ena='0' then cqi:=(others =>'0'); end if; end if; outy <=cqi; end process;end behv;- 4位10进计数器library ieee;use ieee.std_logic_1164.all;entity cnt10_4 isport(fx,rst,ena,clk:in std_logic;d:out std_logic_vector(15 downto 0); led_a:out std_logic);end entity;architecture on

5、e of cnt10_4 iscomponent cnt10 port (rst,fx,ena:in std_logic; cout: out std_logic; outy :out std_logic_vector(3 downto 0);end component;component led_heheport(ena,clk:in std_logic;q:out std_logic);end component;signal e:std_logic_vector(3 downto 0);begin- 整体使用相同的rst和ena，fx作为进位使用。u1:cnt10 port map(fx

6、=>fx,rst=>rst,ena=>ena,cout=>e(0),outy=>d(3 downto 0);u2:cnt10 port map(fx=>e(0),rst=>rst,ena=>ena,cout=>e(1),outy=>d(7 downto 4);u3:cnt10 port map(fx=>e(1),rst=>rst,ena=>ena,cout=>e(2),outy=>d(11 downto 8);u4:cnt10 port map(fx=>e(2),rst=>rst,ena=&g

7、t;ena,cout=>e(3),outy=>d(15 downto 12);u5:led_hehe port map(ena=>e(3),clk=>clk,q=>led_a);end architecture one;- 16位锁存器 latch=闩library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity latch4 isport(d:in std_logic_vector(15 downto 0);ena,clk:in std_logic;q:out std

8、_logic_vector(15 downto 0);end latch4;architecture one of latch4 isbegin process(clk,ena,d) variable cqi:std_logic_vector(15 downto 0); begin if ena='0' then cqi:=cqi;- ena=0 锁存上次的数据 elsif clk'event and clk='1' then cqi:=d;-clk=1&&ena=1 计入新数据 end if; q<=cqi; end proces

9、s; end one;- 报警led hehelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led_hehe isport(ena,clk:in std_logic;q:out std_logic);end led_hehe;architecture one of led_hehe isbegin process(clk,ena) variable cqi:std_logic; begin if ena='0' then cqi:=cqi;- ena=0 锁存上次的

10、数据 elsif clk'event and clk='1' then cqi:= not cqi;-clk=1&&ena=1 计入新数据 end if; q<=cqi; end process;end one;- LED控制模块(数码管controller)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led_controller isport(d:in std_logic_vector(3 downto 0);a:out std_l

11、ogic_vector(6 downto 0);end led_controller;architecture one of led_controller isbegin process(d) begin case d is when "0000"=> a<="1000000"when "0001"=> a<="1111001" when "0010"=> a<="0100100"when "0011"=> a&l

12、t;="0110000" when "0100"=> a<="0011001"when "0101"=> a<="0010010" when "0110"=> a<="0000010"when "0111"=> a<="1111000" when "1000"=> a<="0000000"when "1001

13、"=> a<="0010000" when "1010"=> a<="0001000"when "1011"=> a<="0000011" when "1100"=> a<="1000110"when "1101"=> a<="0100001" when "1110"=> a<="0000110"

14、when "1111"=> a<="0001110" when others=> null; end case; end process;end;- 控制模块(每隔一次clk，就翻转ena和rst)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control is port (clk:in std_logic; rst,ena: out std_logic);end control;architecture behv of

15、control isbegin process (clk) variable cqi :std_logic_vector(2 downto 0); begin if clk'event and clk='1' then if cqi <1 then cqi:=cqi+1;ena<='1'rst<='0' elsif cqi=1 then cqi :=(others =>'0'); ena<='0'rst<='1' end if; end if; end p

16、rocess;end behv;- 时钟（1hz）发生器library ieee;use ieee.std_logic_1164.all;entity freq_div is port (clk:in std_logic; clk_out:out std_logic); end freq_div;architecture fwm of freq_div isconstant m: integer:= 25000;signal tmp:std_logic;begin process(clk,tmp) variable cout:integer:=0; begin if clk'event

17、 and clk='1' then cout:=cout+1; if cout<=m then tmp<='0' elsif cout<m*2 then tmp<='1' else cout:=0; end if; end if; end process;clk_out<=tmp;end fwm;- 总体例化语句：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;- clk是50hz的板载时钟信号，即参考信号，而fx才是测

18、量的输入信号entity voc isport(clk:in std_logic;fx:in std_logic;ledout:out std_logic_vector(28 downto 0);- 数码管7*4end entity;architecture one of voc iscomponent freq_div port (clk:in std_logic; clk_out:out std_logic);end component;component control port (clk:in std_logic; rst,ena: out std_logic);end compone

19、nt;component cnt10_4port(clk,fx,rst,ena:in std_logic;d:out std_logic_vector(15 downto 0); led_a:out std_logic);end component;component latch4port(d:in std_logic_vector(15 downto 0);ena,clk:in std_logic;q:out std_logic_vector(15 downto 0);end component;component led_controllerport(d:in std_logic_vect

20、or(3 downto 0);a:out std_logic_vector(6 downto 0);end component;signal x,z:std_logic;signal g,h:std_logic_vector(15 downto 0);signal leds:std_logic_vector(28 downto 0);signal clk_base:std_logic;beginu1: freq_div port map(clk=>clk,clk_out=>clk_base);u2: control port map(clk=>clk_base,ena=>x,rst=>z);u3: cnt10_4 port map(fx=>fx,rst=>z,ena=>x,d=>g,led_a=>leds(28),clk=>clk_base);u4: latch4 port map(clk=>clk_base,ena=>x,d=>g,