内存基本知识DRAM工作原理

1、Ramaxel Technology LimitedRamaxel Technology LimitedConfidential Dynamic Random Access Memory Each cell is a capacitor + a transistor Very small size SRAM uses six transistors per cell Divided into banks, rows & columns Each bank can be independently controlledDRAMRamaxel Technology LimitedRamax

2、el Technology LimitedConfidentialMain MemoryEverything that happens in the computer is resident in main memoryCapacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanosecondsWhy DRAM for Main Memory ? Cost effective (small chip area than SRAM) High Speed(than HDD, fla

3、sh) High Density(Gbyte) Mass Production Main memoryRamaxel Technology LimitedRamaxel Technology LimitedConfidentialNotation: K, M, G In standard scientific nomenclature, the metricmodifiers K, M, and G to refer to factors of 1,000,1,000,000 and 1,000,000,000 respectively. Computer engineers have ado

4、pted K as thesymbol for a factor of 1,024 (210 ) K: 1,024 (210 ) M: 1,048,576 (220 ) G: 1,073,741,824 (230 ) DRAM density 256M-bit 512M-bitRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM DensityRamaxel Technology LimitedRamaxel Technology LimitedConfidentialWhat is a DRAM? DRAM

5、stands for Dynamic Random Access Memory. Random access refers to the ability to access any of the information within the DRAM in random order. Dynamic refers to temporary or transient data storage.Data stored in dynamic memories naturally decays over time.Therefore, DRAM need periodic refresh operat

6、ion to prevent data loss.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMemory: DRAM position Semiconductor memory device ROM: Non volatile Mask ROM EPROM EEPROM Flash NAND: low speed, high density NOR: high speed, low density RAM: Volatile DRAM: Dynamic Random Access Memory SRAM: S

7、tatic Random Access Memory Pseudo SRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Trend : Future High Speed- DDR(333MHz500MHz), DDR2(533800Mbps), DDR3(8001600Mbps)- Skew-delay minimized circuit/logic : post-charge logic, wave-pipelining- New Architecture : multi-bank structu

8、re, high speed Interface Low Power- 5.5V = 3.3V(sdr) = 2.5V(ddr) = 1.8V(ddr2) = 1.5v (ddr3) = 1.2v?- Small voltage swing I/O interface : LVTTL to SSTL, open drain- Low Power DRAM(PASR, TCSR, DPD) High Density- Memory density: 32MB = 64MB = . 1GB = 2GB = 4GB- application expansion : mobile, memory DB

9、 for shock (than HDD)- Process shrink :145nm(03) =120nm(04) = 100nm = 90nm = 80nm Other Trends- Cost Effectiveness, Technical Compatibility, Stability, Environment. ReliabilityRamaxel Technology LimitedRamaxel Technology LimitedConfidentialStatic RAM SRAM Basic storage element is a 4 or 6 transistor

10、 circuit which will hold a 1 or 0 as long as the system continues to receive power No need for a periodic refreshing signal or a clock Used in system cache Fastest memory, but expensiveSRAM ElementEnable Line/Bit LineBit LineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDynamic RAM

11、 DRAM Denser type of memory Made up of one-transistor (1-T) memory cell which consists of a single access transistor and a capacitor Cheaper than SRAM Used in main memory More complicated addressing schemeDRAM CellWord LineBit LineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRefre

12、sh in DRAMsCapacitor leaks over time, the DRAM must be “REFRESHED”. DRAM CellWord LineBit LineCapacitance LeakageRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSRAM vs. DRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology L

13、imitedConfidentialDRAM Lead Frame and Wire bondingRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidential SDRAM has the multi bank architecture. Conventional DRAM was product that have single bank architecture.

14、 The bank is independent active. memory array have independent internal data bus that have same width as external data bus. Every bank can be activating with interleaving manner. Another bank can be activated while 1st bank being accessed. (Burst read or write)Multi Bank ArchitectureRamaxel Technolo

15、gy LimitedRamaxel Technology LimitedConfidentialDRAM Multi Bank ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Single Bank ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRA

16、M Block Diagram(1)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Block Diagram(2)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Core ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM AddressRamaxel Technology LimitedRamaxel T

17、echnology LimitedConfidentialDRAM Core ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidential16bit DRAM CoreRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Data PathRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM 1T-1C structureRamaxel

18、Technology LimitedRamaxel Technology LimitedConfidentialuRAS: row address strobeuCAS: column address strobeuWE: write enableuAddress: code to select memory cell locationuDQ (I/O): bidirectional channel to transfer and receive datauDRAM cell: storage element to store binary data bituRefresh: the acti

19、on to keep data from leakageuActive: sense data from DRAM celluPre charge: standby stateDRAM Key wordRamaxel Technology LimitedRamaxel Technology LimitedConfidential DRAM cell array consist of so many cells. One transistor & One capacitor Small sense amplifier Low input gain from charge sharingC

20、S : Small storage capacitor: 25fFCBL : Large parasitic capacitor: over 100fFVc: Storage voltageVCP : half Vc for plate biasVBLP : half Vc for BL pre charge bias(initial bias)DRAM CellRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Array Overview Simplified ExampleBITLINE 0BITLIN

21、E 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITRamaxel Technology LimitedRamaxel Technology LimitedConfidentialActiv

22、ating a Row Activating a Row Must be done before a read or write Just latch the row address and turn on a single wordlineBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRE

23、CHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITRamaxel Technology LimitedRamaxel Technology LimitedConfidentialWriting Writing A row must be active Select the column address Drive the data through the column mux Stores the charge on a single capacitorBITLINE 0BITLINE 0#BITLINE 1B

24、ITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITZEROONERamaxel Technology LimitedRamaxel Technology LimitedConfidentialReading Read

25、ing A row must be active Select the column address The value in the sense-amplifier is driven back outBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINE

26、WORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITZEROONERamaxel Technology LimitedRamaxel Technology LimitedConfidentialThe Sense-Amplifier Sense-Amplifier A pair of cross-coupled inverters Basically an SRAM element Weaker than the column mux Write data will “outmuscle” the sense-amplifier Keeps the

27、data at full levelBITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialPrechargePrecharge Inactive state (no wordlines active) Precharge control line high Ties the two sides of the sense-amp together This makes the bitlines stay at VDD/2 Only

28、stable as long as the precharge control line is highotherwise this is unstable! No capacitors connectedBITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialActivation RevisitedActivation Turn off the precharge control line Makes the sense-amp

29、unstableit wants to go to either 0 or 1 instead of staying at VDD/2 A very very very short time later, turn on the wordline of the row to be activated. Couples the capacitor onto the bitlines This “tips” the bitlines to hold the stored value. The sense-amp amplifies the capacitor back to full value.

30、 (hence the name!)BITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Refresh Because the stored memory value is stored on a capacitor (that has resistive leakage), the memory is constantly “forgetting” its contents. Eventually, the char

31、ge on the capacitor wont be enough to tip the sense-amp in the right direction. But, activating a row restores the cells on that row to their full value. There is an explicit refresh command that just activates and immediately deactivates a row. The DRAM has an internal counter that contains the nex

32、t row to be refreshed and increments every time a refresh command is issued.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Refresh Data Retention Time DRAM Cell consists of capacitance which has leakage as time Retention time is period for maintaining its data especially 1 data

33、 Usually, DRAM Cell refresh period is 64ms Refresh Timing tREF : Real cell retention time (Device characteristic), ex) 90ms(Hot) tRFC : Refresh command operating time, ex) 75ns Refresh Spec. Burst Refresh : 64ms Distribute refreshRamaxel Technology LimitedRamaxel Technology LimitedConfidentialAUTO R

34、efresh When this command is input from the IDLE state, the synchronous DRAM starts autorefresh operation. During the auto-refresh operation, refresh address and bank select address are generated inside the Synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accor

35、dingly, 8192times are required to refresh the entire memory. Before executing the auto-refresh command, all the bank must be IDLE state. In addition, since the Precharge for all bank is automatically performed after auto-refresh, no Precharge command is required after auto-refresh.Ramaxel Technology

36、 LimitedRamaxel Technology LimitedConfidentialSelf Refresh Self-Refresh EntrySELF : When this command is input during the IDLE state, the Synchronous DRAM starts self-refresh operation. After the execution of this command, selfrefresh continues while CKE is Low. Since self-refresh is performed inter

37、nally and automatically, external refresh operations are unnecessary. Self-Refresh ExitSELFX : When this command is executed during self-refresh mode, the Sync DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the Sync DRAM enters the IDLE state., no Precharge command is re

38、quired after auto-refresh.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMode Register Special command to initialize the DRAM Burst length Interleaving CAS Latency (read command to read data in clocks) For DDR, DLL reset is also hereRamaxel Technology LimitedRamaxel Technology Limit

39、edConfidentialMRS Block DiagramRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMode Register Because the stored memory value is stored on aRamaxel Technology LimitedRamaxel Technology LimitedConfidentialExtended Mode Register Special command to initialize DDR DRAM DDR onlydont use fo

40、r SDR DLL Enable Drive StrengthRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Interface Command Signals CAS#, RAS#, WE#, CS# CS# + CAS# = Read CS# + WE# + CAS# = Write CS# + RAS# + CAS# = Refresh CS# + RAS# = Activate CS# + WE# = Burst Stop CS# + WE# + RAS# = Precharge CS# + WE

41、# + CAS# + RAS# = MRS or EMRS All others: NOP Other signals: CLK, DATA , DQSRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Interface All signals go from the host to the memory except DQS and data which are bi-directional.Ramaxel Technology LimitedRamaxel Technology LimitedConfi

42、dentialRead Cycle Typical Read Cycle Burst Length 4 CAS Latency = 3Setup TimeHold TimeCAS LatencyCLKCAS#DQSDATADQS delayed to simulate what the NV controller does.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialWrite Cycle Typical Write Cycle Burst Length 4 Write latency is always ze

43、roSetup TimeHold TimeCLKCAS#DQSDATARamaxel Technology LimitedRamaxel Technology LimitedConfidentialData Clocking CLK is always driven by the host DQS is driven by whoever is driving the data NV chip drives on write cycles Memory chip drives on read cycles This scheme is called “source-synchronous cl

44、ocking” Eliminates a lot of the timing headaches from SDR Adds marginRamaxel Technology LimitedRamaxel Technology LimitedConfidentialLatencies All kinds Activate to Precharge Last write data to precharge Activate to Read Activate to Write Refresh cycle time Refresh interval Minimum row active time Y

45、adda yadda yadda Controlled by PFB_TIMING0, PFB_TIMING1, PFB_TIMING2Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialWrite CycleRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDLLsA DLL is a Delay-Locked Loop No transistor can switch in zero time, so there will be a delay between clock and DQS on reads But, it would make it easier if DQS