VHDL程序设计题

1、VHDL程序设计题四、编程题（共50分）1、请补全以下二选一VHDL程序(本题10分)Entity mux is port(d0,d1,sel:in bit;q:out BIT );(2)end mux;architecture connect of MUX is(4)signal tmp1, TMP2,tmp3:bit;(6)begincale:blockbegintmp1<=d0 and sel;tmp2<=d1 and (not sel) tmp3<= tmp1 and tmp2; q <= tmp3;(8)end block cale;end CONNECT;(

2、10)2、编写一个2输入与门的VHDL程序，请写出库、程序包、实体、构造体相关语句，将端口定义为标准逻辑型数据结构（本题10分）y(2)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY nand2 ISPORT (a, b:IN STD_LOGIC;(4)y:OUT STD_LOGIC);(6)END nand2;ARCHITECTURE nand2_1 OF nand2 IS(8)BEGINy <= a NAND b; 一与 y <=NOT( a AND b);等价 (10) END nand2_1;3、根据下表填写完成一个3-8线译

3、码器的VHDL程序(16分)。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder_3_to_8 ISPORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC;y:OUT STD LOGIC VECTOR(7 DOWNTO 0);(2)END decoder_3_to_8;ARCHITECTURE rtl OF decoder_3_to_8 ISSJGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0);(4)BEGIN indata <= c & b & a;( 6)PR

4、OCESS (indata,g1,g2a,g2b) BEGIN IF (g1 = '1' AND g2a = '0' AND g2b = '0' ) THEN( 8)CASE indata ISWHEN "000"=> y <= "11111110"WHEN "001" => y <= "11111101"WHEN "010" => y <= "11111011”;(10)WHEN "011&

5、quot; => y <= "11110111"WHEN "100" => y <= "11101111"WHEN "101" => y <= "11011111"WHEN "110" => y <= "10111111"(12)WHEN "111" => y <= "01111111"WHEN OTHERS=> y <= "XXXXX

6、XXX" END CASE;ELSEy <= "11111111"；(J)END IF;END PROCESS;(16)END rtl;选jffl 瓶入二选（M 愉入蛔聚用码制t HI 1*al麻有ffZbehAyOyly3X4y5yiaXXXXXI1I11111XX1XXX111111GX1 X1 KX1111J111QcQQQl111111 11oOo口11o11I13111。QoI0：I 10 1111110蜡0! 111110i1111ao1oo111I011IIoo1o11i1111a1110Q11oi111o1 11J0口1111111l1o4、

7、三态门电原理图如右图所示，真值表如左图所示，请完成其VHDL程序构造体部分。（本题14分）表三态门真值表控制埼人敷为脑曲din量口X0z0 J011J1S 7-12 二意门电路LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISPORT(din,en:IN STD_LOGIC;dout : OUT STD_LOGIC);END tri_gate ;ARCHITECTURE zas OF tri_gate ISBEGINPROCESS (din,en)BEGINIF (en= 1') THEN dout <= din

8、;ELSE dout <= Z'END IF;END PROCESS ;END zas ;四、编程题（共50分）1、根据一下四选一程序的结构体部分，完成实体程序部分(本题 8分)entity MUX4 isport(2)s:in std logic vector(1 downto 0);(4)d:in std logic vector(3 downto 0);(6)y: out std logic(8)工end MUX4;architecture behave of MUX4 is begin process(s)beginif (s="00") theny&

9、lt;=d(0);elsif (s="01") theny<=d(1);elsif (s="10") theny<=d(2);elsif (s="11") theny<=d(3);elsenull;end if;end process;end behave;2、编写一个数值比较器VHDL程序的进程(不必写整个结构框架)，要求使能信号g低电平时比较器开始工作，输入信号p = q,输出equ为'0',否则为1'。(本题10分)process(p,q)(2)beginif g='0'

10、 then(4)if p = q thenequ <= '0'(6)elseequ <= '1'(8)end if;elseequ <= '1'(10)end if;end process;3、填写完成一个 8-3线编码器的VHDL程序(16分)。Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity eight_tri isport(b: in std_logic_v

11、ector(7 downto 0);( 2)en: in std_logic;y: out std_logic_vector(2 downto 0)(4);end eight_tri;architecture a of eight tri is(6)signal sel: std_logic_vector(8 downto 0); begin sel<=en & b;(8)y<= "000” when (sel= " 100000001 " )else 001" when (sel= " 100000010 " )

12、else(10)“010”when(sel="100000100")else“011”when(sel="100001000")else"100" when (sel=)00f0000" )else(12)“101”when(sel="100100000")else110" when (sel= " 101000000 " )else(14)"111" when (seU0000000" )else(16)»zzz ;end a;4、图

13、中给出了 4位逐位进位全加器，请完成其 VHDL程序。（本题16分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity full_add isport (a,b:in std_logic_vector (3 downto 0);(2)carr:inout std_logic_vector (4 downto 0);sum:out std_logic_vector (3 downto 0);end full_add;architec

14、ture full_add_arch of full_add iscomponent adder(4)port (a,b,c:instd_logic;carr:inoutstd_logic;sum:)outstd_logic(6);end component;begincarr(0)<='0'u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1);(8) (10)u2:adder port map(a(2),b(2),carr

15、(2),carr(3),sum(2);(12)u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);(14) (16)end full_add_arch;四、编程(共50分)1、完成下图所示的触发器。(本题10分)CLRQCLKDQNlibrary IEEE;use IEEE.std_logic_1164.all;entity VposDff isport (CLK, CLR, D: inSTD_LOGIC;2 分Q, QN: out STD LOGIC );4 分end VposDff;architecture VposDff_arch of

16、VposDff isbeginprocess ( CLK, CLR )6 分begin if CLR='1' then Q <= '0' QN <='1'elsif CLK'event and CLK='1' thenQ <= D; QN <= not D;8 分end if;end process;10 分end VposDkarch;2、完成以下4位全加器代码(本题 10分) library IEEE;use IEEE.std_logic_1164.all;entity full_add is

17、port (a,b:instd_logic_vector (3 downto 0);cin:instd_logic;cout:out std_logic;sum:outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add is component adderport (a,b,c:instd_logic;carr:outstd_logic;sum:outstd_logicend component;signal c1,c2,c3: std_logic;beginu0:adder por

18、t map(a(0),b(0),cin,c1,sum(0);4 分u1:adder port map(a,b(1),c1,c2,sum(1);5 分u2:adder port map(a(2),b(2),c2,c3,sum(2);6 分u3:adder port map(a(3),b(3),c3,cout,sum(3);10 分end full_add_arch;3、补充完整如下代码，使之完成4状态不断循环。(本题10分)ARCHITECTURE arc OF ss IStype states is ( st0,st1,st2,st3 );2 分signal outc: states;4 分B

19、EGINPROCESS(clk)BEGINIF reset='1' thenoutc <=st0 :6 分elsif clk'event and clk='1' thenCASE outc ISWHEN st0 => outc <= st1;7分WHEN st1 => outc <= st2;8分WHEN st2 => outc <= st3;9分WHEN st3 => outc <= st0;10 分WHEN OTHERS => outc <=st0;END CASE;end if;EN

20、D PROCESS;END arc;4、设计异或门逻辑：（本题20分）如下异或门，填写右边的真值表。（此项5分）ABYL一00o11101L1J其表达式可以表不为:这一关系图示如下：（此项试编写完整的 VHDL代码实现以上逻辑。可以采用任何描述法。（此项10分）library ieee;use ieee.std_logic_1164.all;entity yihuo1 isport( a,b :in std_logic; y :out std_logic );end yihuo1;architecture yihuo1_behavior of yihuo1 is beginy<=a xo

21、r b;（第2种写法）process(a,b) beginif a=b theny<='0' elsey<='1'end if;10分end process;end yihuo1_behavior;四、编程（共50分，除特殊声明，实体可只写出PORT语句，结构体要写完整）1、用IF语句编写一个二选一电路，要求输入 a、b, sel为选择端，输出q。（本题10分）Entity sel2 isPort (a,b : in std_logic;sel : in std_logic;q : out std_logic);End sel2;(3)Archite

22、cture a of sel2 is beginif sel = 0'then(6)(9)(10)q <= a;elseq <= b;end if;end a;2、编写一个4位加法计数器 VHDL程序的进程（不必写整个结构框架），要求复位信号reset低电平时计数器清零，变高后，在上升沿开始工作；输入时钟信号为clk,输出为q。（本题10分）Process（reset,clk）（2）beginif reset = 0 'thenq <= 0000"；(4)elsif clk 'event and clk = 1' then (6)q

23、<= q + 1;(9)end if;end process;(10)3、填写完成一个8-3线编码器的真值表(5分)，并写出其VHDL程序(10分)。8 -3线编码器真值表enby0y1y21000000000001000000100011000001000101000010000111000100001001001000001011010000001101100000001110xxxxxxxx高阻态entity eight_tri isport(b: in std_logic_vector(7 downto 0);en: in std_logic;y: out std_logic_v

24、ector(2 downto 0);end eight_tri;(3) architecture a of eight_tri issignal sel: std_logic_vector(8 downto 0);(4)beginsel<=en & b;y<=“ 000 ”when (sel=” 100000001 ”)else“ 001 ”when (sel=” 100000010 ”)else“010”when (sel=” 100000100 ”)else“ 011 ”when (sel=” 100001000 ”)else“100”when (sel=1000100

25、00)else“101”when (sel=100100000)else“110”when (sel=101000000)else“111”when (sel=110000000)else (9)«”zzz ;(10)end a;VHDL程序。4、根据已给出的全加器的VHDL程序，试写出一个4位逐位进位全加器的(本题15分)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity adder isport (a,b,c:in

26、std_logic;carr:inout std_logic;sum:out std_logic);end adder;architecture adder_arch of adder isbeginsum <= a xor b xor c;carr <= (a and b) or (b and c) or (a and c);end adder_arch;entity full_add isport (a,b:in std_logic_vector (3 downto 0);carr:inout std_logic_vector (4 downto 0);sum:out std_

27、logic_vector (3 downto 0);end full_add;(5)architecture full_add_arch of full_add iscomponent adderport (a,b,c:in std_logic;carr:inout std_logic;sum:out std_logic)；end component;(10)begincarr(0)<='0'u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1),b(1),carr(1),carr

28、(2),sum(1);u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);end full_add_arch;(15)四、编程(共50分，除特殊声明，实体可只写出 PORT语句，结构体要写完整)1、用IF语句编写一个四选一电路，要求输入 d0d3, s为选择端，输出 y。(本题10分) entity MUX4 isport(s:in std_logic_vector(1 downto 0);d:in std_logic_vector(3 dow

29、nto 0);y: out std_logic);end MUX4;(3)architecture behave of MUX4 isbeginprocess(s)beginif (s="00") theny<=d(0);(4)elsif (s="01") theny<=d(1);(5)elsif (s="10") theny<=d(2);(6)elsif (s="11") theny<=d(3);(9)(10)elsenull;end if;end process;end behave;2

30、、编写一个数值比较器 VHDL程序的进程(不必写整个结构框架)，要求使能信号g低电 平时比较器开始工作，输入信号p = q,输出equ为'0',否则为1'。(本题10分)process(p,q)(2)beginif g='0' then(4)if p = q thenequ_tmp <= '0'(6)elseequ_tmp <= '1'(8)end if; elseequ_tmp <= '1'(10)end if;end process;3、填写完成一个3-8线译码器的真值表（5分），并写

31、出其VHDL程序（10分）。3-8译码器的真值表ena2a1a0y1000000000011001000000101010000001001011000010001100000100001101001000001110010000001111100000000xxx00000000entity tri_eight isport(a: in std_logic_vector (2 downto 0);en: in std_logic;y: out std_logic_vector (7 downto 0);end tri_eight;(2)architecture a of tri_eight

32、issignal sel:std_logic_vector (3 downto 0);(4)beginsel(0) <= a(0); sel <=a(1); sel(2) <= a(2); sel(3) <= en; (5) with sel selecty <= "00000001" when "00000010" when " "00000100" when "00001000" when "00010000" when "00100000" when "01000000" when "10000000" when "00000000" when end a;1000",1001&q