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1、14位二进制并行加法器的源程序ADDER4B.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER4B IS -4位二进制并行加法器 PORT(CIN:IN STD_LOGIC; -低位进位 A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -4位加数 B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -4位被加数 S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -4位和 CONT: OUT STD_L

2、OGIC); END ADDER4B;ARCHITECTURE ART OF ADDER4B IS SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL AA,BB: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN AA<='0'& A; -将4位加数矢量扩为5位,为进位提供空间 BB<='0'& B; -将4位被加数矢量扩为5位,为进位提供空间 SINT<=AA+BB+CIN ; S<=SINT(3 DOWNTO 0); CONT<=SINT(4)

3、;END ART;2 8位二进制加法器的源程序ADDER8B.VHDLIBRARY IEEE;USE IEEE_STD.LOGIC_1164.ALL;USE IEEE_STD.LOGIC_UNSIGNED.ALL:ENTITY ADDER8B IS -由4位二进制并行加法器级联而成的8位二进制加法器 PORT(CIN:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT:OUT STD_LOGIC);

4、END ADDER8B;ARCHICTURE ART OF ADDER8B IS COMPONENET ADDER4B -对要调用的元件ADDER4B的界面端口进行定义 PORT(CIN:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CONT:OUT STD_LOGIC);END COMPONENT ;SIGNAL CARRY_OUT:STD_LOGIC; -4位加法器的进位标志BEGIN U1:ADD

5、ER4B -例化(安装)一个4位二进制加法器U1 PORT MAP(CIN=>CIN,A=>A(3 DOWNTO 0),B=>B(3 DOWNTO0), S=>S(3 DOWNTO 0),COUT=>CARRY_OUT);U2:ADDER4B -例化(安装)一个4位二进制加法器U2 PORT MAP(CIN=>CARRY_OUT,A=>A(7 DOWNTO 4),B=>B(7 DOWNTO 4), S=>S (7 DOWNTO 4);CONT=>CONT);END ART;3.触发器和缓冲器D触发器:Process(clk) begi

6、n if(clkevent and clk=1) then q <= d; end if;end process; 缓冲器:Process(clk)begin if(clk=1) then q <= d; end if;end process; T触发器:Process(clk)begin if(clkevent and clk=1) then if(t = 1) then q <= not(q); else q <= q; end if; end if;end process; 4.16位锁存器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1

7、164.ALL;ENTITY REG16B IS -16位锁存器 PORT (CLK:IN STD_LOGIC; -锁存信号 CLR:IN STD_LOGIC; -清零信号 D:IN STD_LOGIC_VECTOR (8 DOWNTO 0) -8位数据输入 Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);-16位数据输出END REG16B;ARCHITECTURE ART OF REG16B IS SIGNAL R16S:STD_LOGIC_VECTOR(15 DOWNTO 0); -16位寄存器设置BEGINPROCESS (CLK,CLR) BEGIN IF C

8、LR = '1' THEN R16S<= "0000000000000000";-异步复位信号 ELSIF CLK'EVENT AND CLK = '1' THEN-时钟到来时,锁存输入值 R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);-右移低8位 R16S(15 DOWNTO 7)<=D; -将输入锁到高能位 END IF; END PROCESS; Q<=R16S;END ART;58位右移寄存器的源程序SREG8B.VHDLIBRARY IEEE;USE IEEE.STD_LOGI

9、C_1164.ALL; -8位右移寄存器ENTITY SREG8B IS PORT (CLK:IN STD_LOGIC; LOAD :IN STD _LOGIC; BIN:IN STD_LOGIC_VECTOR(7DOWNTO 0); QB:OUT STD_LOGIC );END SREG8B;ARCHITECTURE ART OF SREG8B IS SIGNAL REG8B:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS (CLK,LOAD) BEGIN IF CLK'EVENT AND CLK= '1' THEN IF LO

10、AD = '1' THEN REG8<=DIN; -装载新数据 ELSE REG8(6 DOWNTO0)<=REG8(7 DOWNTO 1);-数据右移 END IF; END IF; END PROCESS; QB<= REG8 (0); -输出最低位END ART;68位乘法器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; -8位乘法器顶层设计ENTITY MULTI8X8 IS PORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC;-乘法启动信号,高电平复位与加载,低电平运算 A:

11、IN STD_LOGIC_VECTOR(7 DOWNTO 0); -8位被乘数 B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); -8位乘数 ARIEND:OUT STD_LOGIC; -乘法运算结束标志位 DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);-16位乘积输出END MULTI8X8;ARCHITECTURE ART OF MULTI8X8 IS COMPONENT ARICTL -待调用的乘法控制器端口定义 PORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC; CLKOUT:OUT STD_LOGIC

12、;RSTALL:OUT STD_LOGIC; ARIEND:OUT STD_LOGIC);END COMPONENT;COMPONENT ANDARITH -待调用的控制与门端口定义 PORT(ABIN:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT:OUT_STD_LOGIC_VECTOR( 7 DOWNTO 0) );END COMPONENT;COMPONENT ADDER8B -待调用的8位加法器端口定义COMPONENT SREG8B -待调用的8位右移寄存器端口定义 COMPONENT REG16B -待调用的16右移

13、寄存器端口定义 SIGNAL GNDINT:STD_LOGIC;SIGNAL INTCLK:STD_LOGIC;SIGNAL RSTALL:STD_LOGIC;SIGNAL QB:STD_LOGIC;SIGNAL ANDSD:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL DTBIN:STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL DTBOUT:STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINDOUT<=DTBOUT;GNDINT<= '0';U1:ARICTL PORT MAP(CLK=>

14、CLK, START=>START, CLKOUT=>INTCLK, RSTALL=>RSTALL, ARIEND=>ARIEND); U2:SREG8B PORT MAP(CLK=>INTCLK, LOAD=>RSTALL. DIN=>B, QB=>QB);U3:ANDARITH PORT MAP(ABIN=>QB,DIN=>A,DOUT=>ANDSD);U4:ADDER8B PORT MAP(CIN=>GNDINT,A=>DTBOUT(15 DOWNTO 8), B=>ANDSD, S=>DTBIN(

15、7 DOWNTO 0),COUT =>DTBIN(8);U5:REG16B PORT MAP(CLK =>INTCLK,CLR=>RSTALL, D=>DTBIN, Q=>DTBOUT);END ART;7有时钟使能的十进制计数器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; -有时钟使能的十进制计数器ENTITY CNT10 ISPORT (CLK:IN STD_LOGIC; -计数时钟信号 CLR:IN STD_LOGIC; -清零信号 END:IN STD_LOGIC; -计数使能信号 CQ:OUT INTEGER

16、 RANGE 0 TO 15;-4位计数结果输出 CARRY_OUT:OUT STD_LOGIC); -计数进位 END CNT10;ARCHITECTURE ART OF CNT10 IS SIGNAL CQI :INTEGER RANGE 0 TO 15;BEGIN PROCESS(CLK,CLR,ENA) BEGIN IF CLR= '1' THEN CQI<= 0; -计数器异步清零 ELSIF CLK'EVENT AND CLK= '1' THEN IF ENA= '1' THEN IF CQI<9 THEN CQI

17、<=CQI+1; ELSE CQI<=0;END IF; -等于9,则计数器清零 END IF; END IF; END PROCESS; PROCESS (CQI) BEGIN IF CQI=9 THEN CARRY_OUT<= '1'; -进位输出 ELSE CARRY_OUT<= '0';END IF; END PROCESS; CQ<=CQI;END ART;8) 六进制计数器的源程序CNT6.VHD(十进制计数器的源程序CNT10.VHD与此类似)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.A

18、LL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 ISPORT (CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA: IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT: OUT STD_LOGIC );END CNT6;ARCHITECTURE ART OF CNT6 ISSIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,CLR,ENA)BEGIN IF CLR='1'

19、THEN CQI<="0000"; ELSIF CLK'EVENT AND CLK='1' THEN IF ENA='1' THEN IF CQI=“0101” THEN CQI<=“0000”; ELSE CQI<=CQI+'1';END IF; END IF; END IF; END PROCESS; PROCESS(CQI) BEGIN IF CQI=“0000” THEN CARRY_OUT<='1'; ELSE CARRY_OUT<='0';END

20、 IF; END PROCESS; CQ<=CQI;END ART;9十进制计数器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY count10 ISPORT(clk: IN STD_LOGIC; seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END count10;ARCHITECTURE a1 OF count10 ISsignal sec: STD_LOGIC;signal q : STD_LOGIC_VECTOR(21 DOWNTO 0);

21、signal num: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINprocess(clk) -get 1 hz clock pulsebeginif clk'event and clk='1' then q<=q+1; end if;sec<=q(21); -get 1 hz clock pulseend process;timing: process(sec) beginif sec'event and sec='1' then if num<9 then num<=num+1; else nu

22、m<="0000" end if;end if;end process;B1: block -bcd-7segsBegin -gfedcba seg<= "0111111" when num=0 else "0000110" when num=1 else "1011011" when num=2 else "1001111" when num=3 else "1100110" when num=4 else "1101101" when nu

23、m=5 else "1111101" when num=6 else "0000111" when num=7 else "1111111" when num=8 else "1101111" when num=9 else "0000000"end block;END a1;104MHz到1Hz的分频器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY count ISPORT( clk

24、: in STD_LOGIC; q: out STD_LOGIC;END count;ARCHITECTURE a OF count ISsignal tmp: STD_LOGIC_vector(21 downto 0);Beginprocess(clk) beginif clk'event and clk='1' then tmp<=tmp+1;end if;end process;q<=tmp(21);END a;11与门ENTITY shili2 is port ( input1 : in std_logic; inptu2 : in std_logi

25、c; output1 : out std_logic );end entity;architecture one of shili2 is begin output1<=input1 and input2; end entity;12.四输入与门电路library ieee;use ieee.std_logic_1164.all;entity and4 is port(a,b,c,d:in std_logic; y:out std_logic;end and4; architecture and4_1 of and4 is begin y<= a and b and c and d

26、;end nand4_1;法二(与非门):library ieee;use ieee.std_logic_1164.allentity nand4 is port(a.b,c,d:in std_logic; y:out std_logic);end nand4;architecture nand4_2 of nand4 si begin p1:process(a,b,c,d) variable tmp:std_logic_vector(3 downto 0);begin tmp:=a&b&c&d;case tmp is when"0000"=>

27、y<='1' when"0001"=>y<='1' when"0010"=>y<='1' when"0011"=>y<='1' when"0100"=>y<='1' when"0101"=>y<='1' when"0110"=>y<='1' when"0111"=>

28、;y<='1' when"1000"=>y<='1' when"1001"=>y<='1' when"1010"=>y<='1' when"1011"=>y<='1' when"1100"=>y<='1' when"1101"=>y<='1' when"1110"=&g

29、t;y<='1' when"1111"=>y<='1' when others=>y<='x'end case;end process;end nand4_2;13四位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity add isport(a,b:in std_logic_vector(3 downto 0);cin:in s

30、td_logic;s:out std_logic_vector(3 downto 0);cout:out std_logic);end add;architecture beh of add isbeginprocess(a,b,cin)ariable x:std_logic_vector(3 downto 0);variable m,n,l:integer; begin m:=conv_integer(a); n:=conv_integer(b); l:=m+n+conv_integer(cin); x:=conv_std_logic_vector(l,4); s<=x(3 downto 0); cout<=x(3); end process;end beh;14N位移位寄存器:158位通用寄存器:16串入串出移位寄存器:1710位计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_L

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