外文翻译---触发器

1、.英文资料及中文翻译FLIP-FLOPS1 IntorduceIn this passage, we show how to design flip-flops, which operate as one-bit memory cells. Flip-flops are also called latches. Logic circuits constructed using flip-flops can have the present output be a function of both the past and present inputs. Such circuits are ca

2、lled senfiential logic circuits. All flip-flops are based on the same principle: Positive feedback is used to produce a circuit that is bistable . A bistable circuit is one that has two stable operating points. Which operating point the circuit is in is called the state of the circuit. If the state

3、can be sensed and changed, then the circuit can function as a one-bit memory element. The simplest bistable circuit is constructed using two inverters in a loop as shown in Figure 11.This circuit only has two nodes, A and B. Because of the inverters, if A is high, B must be low and vice versa; hence

4、, the circuit has two stable states. The operation of the bistable circuit can also be viewed using a plot of the transfer characteristic of the two inverters in series, as shown in Figure 12. Part (a) of the figure shows the static transfer characteristic of one of the inverters. When the input vol

5、tage is below the threshold (a logical ZERO), the output voltage is high (a logical ONE). When the input voltage is greater than the threshold, the output voltage is low. In part (b) of the figure, we show the transfer characteristic that results from putting both inverters in series. Any solution o

6、f the equations for this circuit must also lie on this characteristic. Because of the external connection, the input and output voltages of the series connection of the two inverters must be the same. Therefore, we draw a line with a slope of unity on the plot as well. This line is called the load l

7、ine, because it represents the external load connection for the two inverters in series. Any solution of the equations for this circuit must also lie on the load line. Therefore, when the equations are simultaneously solved, the only possible operating points are found where the straight line inters

8、ects the transfer characteristic. There are three intersections on the plot, but only two of them are stable, as we will now demonstrate.The point where the load line intersects the middle of the transfer characteristic is not stable. To see that this statement is true, suppose for the moment that t

9、he circuit is at this point. If the input voltage increases at all (due to noise or some change in the circuit), the output voltage of the inverters must also increase. But the output is input, so as it increases, it causes further increases in the output, and the original change is magnified. This

10、positive feedback will quickly drive the circuit to the top operating point shown. At that point, the input and output of the two-inverter chain are high and the midpoint (B in Figure 11) is low, so the circuit is stable and can remain in this state forever. If we started at the midpoint and let the

11、 input voltage decrease a bit, we would end up at the lower operating point, which is again stable.In the sections that follow, we show how we can move this bistable circuit from one operating point to the other. The internal positive feedback will then hold the circuit at that state until we delibe

12、rately change it; hence, the circuit has memory.Figure 11A bistable circuit(a)(b)Figure 12 (a) One inverter and its transfer characteristic (b) The transfer characteristic for two inverters in series and the load line for the circuit 2 The Set-Reset Flip-FlopA set-reset (SR) flip-flop is shown in Fi

13、gure 21(a). A table describing the function of the circuit is shown in part (b) of the figure, and the schematic symbol is shown in part (c). This function table is similar to a truth table, but it describes a dynamic situation, not a static one. The output is the output at some discrete time, denot

14、ed by Qn, and the table includes an entry for the previous state of the flip-flop (Qn-1). Although the circuit is drawn differently, the two NOR gates are in series, just like the inverters in Figure 12(b). The configuration shown here is usually described as cross coupled. The flip-flop has two out

15、puts that are complements of each other. We usually consider the Q output to be the state of the flip-flop.(a)SRQn00Qn-101010111不允许的（b）(c) Figure 21 (a) An SR flip-flop, (b) a table describing the circuits function (c) the schematic symbol.The circuit operates in the following way: If both inputs (S

16、 and R) are zero, the previous state is retained. Suppose, for example, that Qn-1 is high (i.e., ONE). Then the output of the bottom NOR, which isn-1 , will be low (i.e., ZERO), independently of what S is. In this case, both inputs to the top NOR are low, so its output is high, as originally assumed

17、. Now suppose that Qn-1 is low. In this case, both inputs to the bottom NOR are low, so n-1 is high. Therefore, the output of the top NOR, Qn-1, will be low, as assumed. Now consider what happens when the set input, S, goes high while R remains low. The output of the bottom NOR, n-1 , will now go lo

18、w, independent of what the previous state of the circuit was. With R low as well, this guarantees that Qn will go high (i.e, the flip-flop has been “set”). Note that S does not have to stay high. Once the flip-flop is set, the S input can go low again, and the state will be retained. This sequence o

19、f events is illustrated in Figure 22 The figure shows that there is some delay through each gate, so it takes a time td for the change at the gate input to affect its output. Figure 22 A timing diagram for the SR flip-flop. The arrows indicate which transition causes the following change.The operati

20、on of the reset input is similar. If R goes high while S is kept low, the output of the top NOR, Qn, will go low (i.e., the flip-flop is “reset”). With Qn and S both low, the bottom NOR output will be high. The reset input can go low again, and this new state will be retained. This sequence is also

21、illustrated in Figure 22.Finally, we note that both inputs should not be allowed to go high at the same time. If this happens, both NOR outputs go low, so Q and are not complements anymore. Also, if both inputs are high and then go low at exactly the same time, we cant predict what the resulting out

22、put state will be, since both outputs will try to go high, which is a condition that cannot be sustained. Which output will actually stay high depends on mismatches in the NOR gates and cannot be predicted.3 The JK Flip-FlopThe fact that the output of an SR flip-flop is undefined if both inputs go h

23、igh is troublesome in many applications. The JK flip-flop avoids this problem and is more flexible in its operation. The JK flip-flop is a clocked flip-flop; that is, it requires a separate clock input to operate. This clock signal is usually a square wave with a fixed period. Logic circuits that re

24、quire a clock and that only allow output transitions to occur in synchrony with the clock are called synchronous-logic circuits. The clock can be generated using an astable multivibrator. (a) (b)JKQn00Qn-101010111n-1 (c) Figure 31 (a) A JK flip-flop made using an SR flip-flop. (b) The Schematic symb

25、ol for a JK flip-flop (c) the function table. (The flip-flop only changes state when the clock is high.)A JK flip-flop is shown in Figure 31(a); the schematic symbol is shown in part (b) of the figure, and the function table is shown in part (c). The AND gates serve to enable the inputs to the SR fl

26、ip-flop. That is, only when the clock is high are the J and K inputs able to affect the SR flip-flop. In addition to needing the clock to be high, the J input affects S only if the SR flip-flop is currently reset, and the K input affects R only if the flip-flop is currently set. Therefore, we see th

27、at when both J and K are low, S and R will be low, and the flip-flop will hold its present state just like the SR flip-flop. When J is high and the flip-flop is currently reset (i.e., n-1 is high), the flip-flop will be set when the clock goes high, independently of what K is. If K is high and the f

28、lip-flop is currently set (i.e., Qn-1 is high), the flip-flop will reset when the clock goes high, independently of what J is. It follows that if both J and K are high, the flip-flop will toggle its state when the clock goes high. When operated in the toggle mode, a JK flip-flop is sometimes called

29、a T flip-flop.The JK flip-flop as shown in Figure 31has a major problem: It will work only if the clock pulse width (i.e., the time the clock is high) is short compared with the propagation delay of the gate. To understand this limitation, consider what happens when J and K are both high and Qn-1 is

30、 low. In this case, the output of the flip-flop will toggle when the clock goes high, as indicated in the function table. But, if the output toggles and the clock is still high, the output will toggle again . This process will repeat until either the clock goes low or J or K changes. In order to avo

31、id this problem, we use master-slave JK flip-flop.A master-slave JK flip-flop is shown in Figure 32. The master flip-flop is enabled when the clock is high, so the data are latched into the master during that portion of the clock cycle. During that time, c is low and the slave is disabled and holds

32、the previous value. Then the clock goes low, c goes high and enables the slave. The data from the master are then transferred to the slave and show up at the output. Since the master and slave flip-flops are never enabled at the same time, the output will not continue to toggle if the clock is held

33、in any one state for too long. The clock does have to remain in each state long enough to allow for the propagation delay through one of the flip-flops.Figure 32 A master-slave JK flip-flopIn designing a master-slave JK flip-flop, we must carefully consider the propagation delays of the individual g

34、ates to prevent the slave from changing before it should. For example, in the figure, the data on SM and RM can change one gate delay after the clock goes high. The slave clock, which is c, goes low one inverter delay after the clock goes high. We must be sure that the slave clock changes before the

35、 output of the master flip-flop can change; otherwise, the data will pass on through to the slave and we will not have accomplished our purpose. Similarly, when the clock goes low, we must be sure that the master is disabled before the slave outputs can change.The JK flip-flop just described is leve

36、l-triggered flip-flop; that is, the master is enabled when the clock level is high, and the slave is enabled when the clock level is low. The problem with level-triggered JK flip-flops is that they are sensitive to glitches on the inputs at certain points in the operation. For example, suppose that

37、the previous state of the flip-flop was Q=0 and that we are now ready for the next clock cycle. Suppose further that J=0 and K=1, so we are resetting the flip-flop again; in other words, we dont want the state to change. In this case, while the clock is high, both SM and RM are low, so the master fl

38、ip-flop output should not change. However, if a positive glitch occurs on the J input prior to the clock going low, it can pass through to SM and set the master flip-flop. Since Q is low, the AND gate driving RM is disabled, so we dont have any opportunity for the flip-flop to be reset. As a result,

39、 when the clock goes low, this error will be passed on to the slave. A similar situation exists if we are trying to set the flip-flop when it is already set. A positive glitch on the K input can cause an erroneous reset. This problem is sometimes called ones catching, since the flip-flop has capture

40、d an erroneous ONE. We could make the problem far less likely to occur if we used a clock with a very short positive pulse, but a much better solution is to use an edge-triggered JK flip-flop.An edge-triggered JK flip-flop is shown in Figure 33(a), and the schematic symbol is shown in part (b) of th

41、e figure. The triangle inside the block in part (b) indicates that the flip-flop is edge-triggered. as explained in a moment, and the bubble indicates that it is negative edge triggered (i.e., the input is latched on the negative-going edge of the clock ). (a) (b) Figure 33 (a) An edge-triggered JK

42、flip-flop (b) the schematic symbol for it To understand how this circuit operates, we need to first examine the input gate structure. Consider, for example, the situation where Q=0 and we want to set the flip-flop, so J=1. Part of the input structure is shown in Figure 34(a) for this case, and the c

43、orresponding waveforms are shown in part (b) of the figure. (a) (b) Figure 34(a) A part of the input circuit when Q=0. (b) The resulting waveforms.The bubbles at the input of the second gate invert the inputs so that the AND is true when both inputs are low. Because Q=0, we know that =1. Now, with J

44、=1, the output of the NAND gate, Jc, will be the inverse of the clock, delayed by one gate delay. Therefore, when the clock goes low, Jc will go high one gate delay later, as shown. During that gate delay, both inputs to the second gate are low, so the AND is true and S goes high. In other words, th

45、e negative edge of the clock has produced a narrow pulse on the S line as a result of the J input being high. Similarly, if the K input is high and Q=1, a negative clock edge will produce a narrow pulse on the R line. In this way, the SR flip-flop is set or reset only on the negative clock edge. As

46、long as the J and K inputs are held constant for some short time prior to the clock edge (called the setup time) and are held constant for some short time after the clock edge (called the hold time), the circuit is insensitive to glitches on the inputs. It is also possible to make positive edge-trig

47、gered circuits4 The D Flip-FlopA D flip-flop is shown is Figure 41(a), and its schematic symbol is shown in part (b) of the figure. This flip-flop implements a digital delay; that is, the output at the end of each clock cycle is equal to the input on the previous cycle, as seen in the function table

48、 in part (c) of the figurehence the name D flip-flop. This particular circuit is positive-edge triggered, so the output changes state slightly after the positive-going edge of the clock. The output is insensitive to the value of the D input, except for a brief time before (the setup time) and after

49、(the hold time) the positive clock edge. D flip-flips are commonly used in shift registers and counters, as discussed in the next section. (a) (b)Dn-1Qn0011 (c) Figure 41 (a) A D flip-flop (b) its schematic symbol (c) the function table. Clocked flip-flops also frequently have asynchronous clear and

50、 preset inputs, as shown for a D flop-flop in Figure 42. The preset input will set the flip-flop so that Q=1 at any time, regardless of the state of the clock; that is what is meant by being asynchronous. In similar fashion, the clear input will clear the flip-flop so that Q=0 at any time. Figure 42

51、 A D flip-flop with preset and clear inputs 触发器1简介本文，我们将介绍如何设计可作为一位存储单元的触发器。触发器也可称为锁存器。采用触发器的逻辑电路结构其当前的输出是电路的前一稳定状态和当前稳定状态的函数。这样的电路称为时序逻辑电路。所有的触发器都遵循同一规则：正反馈用来生成双稳态电路，双稳态电路是一个具有两个稳定工作点的电路。电路所处的工作点称为电路的一个状态。如果其状态能够读出和改变，那么此电路就可以作为一个一位存储器单元。最简单的双稳态电路是在一个回路中利用两个反相器构成的。如图11所示。这个电路只有两个节点，A和B。由于是反相器，所以如果A

52、是高电平,那么B就必须是低电平，或者反相。因此，电路具有两个稳定状态。也可以通过两个串联的反相器的传输特性曲线图来查看双稳态电路的操作，如图12所示。突12（a）给出了其中一个反相器的静态传输特性。当输入电压低于门限电压（逻辑0），输出电压变为高电平（逻辑1）。当输入电压超过门限电压，则输出为低电平。在图12（b），给出了将两个反相器串联后所得到的传输特性曲线。该电路逻辑等式的任何一个结果都必须落在这条特性曲线上。由于是外部连接，两个反相器的串联连接处的输入输出电压必须相等。因此，再在图中划出一条单位斜率的直线。这条线称为负载线，因为它代表了两个串联反相器的外部负载的关系。该电路逻辑等式的任何

53、一个解也必须落在负载线上。因此，如果将这两个等式联立求解，就可以得到唯一的工作点，这一点正是负载直线与传输特性曲线的交点。在图中的曲线上一共有三个交点，但是只有其中两个是稳定的，正如我们将要论证的。图 11双稳态电路 (a) （b） 图 12（a）反相器和它的传输特性 （b）两个反相器串联的传输特性和负载曲线负载直线与传输特性曲线中部的交点是不稳定的。为了证明这点，假设在某一时刻电路工作与这一点。如果无论何时输入电压增加了（由于噪声或是电路发生一些变化），反相器的输出电压也必须增大。但是由于输出就是输入，因此它的增大会导致输出的进一步增加，原有的变化被放大了。这样的正反馈将迅速驱动电路达到所示

54、的顶端的工作点。在那一点，二反相器链的输入输出电压都很高，而中间点电压（图11中的vB）较低。因此电路是稳定的并且能够永远保持着状态。如果从中间点开始让输入电压减小一点，那么会落在更低的工作点上，再次达到稳定。在接下来的部分，我们将说明如何使这个双稳态电路从一个工作状态转移到另一个工作状态，但是，内部的正反馈将会使电路保持在这个状态直到有意改变它。因此电路具有记忆。2 SR触发器SR（设置-复位）触发器如图21（a）所示。图21（b）给出了电路的功能表，而图21(c)给出了它的电路逻辑符号。这个功能表与真值表类似，但它描述的是动态的情况，而不是静态的。其输出是在一些离散时间上的输出，用Qn表示

55、，此外表中还包括触发器前一状态的输入(Qn-1)。虽然所画的电路与上节所讲得不相同，但它也是两个或非门串联在一起，就像图12(b)中的两个反相器一样。这里所示的结构通常也被描述为交叉耦合。触发器的两个输出是互补的。我们通常认为输出Q是触发器的状态。(a)SRQn00Qn-101010111不允许的 （b） (c) 图 21 (a) SR触发器 （b）描述电路的功能表 （c）电路逻辑符号该电路的工作原理如下：如果两个输入端(S和R)都是逻辑0，则保持前一状态。例如，假设Qn-1时高电平（即逻辑1），那么无论S是什么状态，下面那个或非门的输出 n-1 都将是低电平(即逻辑0)。在这种情况下，上面那

56、个或非门的两个输入端都是低电平，因此它的输出是高电平，正如前面所假设的那样。现在，我们假设Qn-1是低电平。在这种情况下，下面那个或非门的两个输入都是低电平，所以其输出 n-1 为高电平。因此，上面那个或非门的输出Qn-1就像假设的那样是低电平。现在考虑当置1端S为高电平而置0端R保持低电平时会发生什么情况。这时无论电路的前一状态是怎样的，下方的或非门的输出 n-1 都将变为低电平。再加上R也是低电平，这就保证了Qn将变为高电平（即触发器被置位为1）。注意，S不必一直处于高电平，一旦触发器被置1，输入端S便可再次回到低电平，状态将被保持。整个过程的顺序在图22中用图解进行了说明。从图中可以看到，在通过每一个门时都有一定的延时。因此，在门输入端的变化需要延迟一个时间td才能影响到输出端。 图22 SR 触发器的时序图 箭头表明此处输入电平的转换引起的随后输出的变化置0输入端的工作原理是类似的。如果R达到高电平而S保持而低电平，那么上面那个或非门的输出Qn将变为低电平（即触发器被置0）。由于Qn和S都为低电平，下方的或非门的输出将为高电平。此时置0端可以再次回到低电平，新的状态将被保持。其顺序在图2