Verilog程序12、VGA显示字符

1、verilog程序12、vga显示字符 verilog程序 本地地址：e:fpgavediovga_charsrcvga_char.v timescale 1ns / 1ps / / company: / engineer: / / create date: 17:15:28 11/27/2021 / design name: / module name: vga_char / project name: / target devices: / tool versions: / description: / 在液晶上显示字符 / dependencies: / / revision: / re

2、vision 0.01 - file created / additional comments: / / module vga_char(clk,rst_n,vsync,hsync,r,g,b); input clk,rst_n; output vsync,hsync; output2:0 r; output2:0 g; output1:0 b; reg vsync,hsync; reg10:0 x_cnt; reg9:0 y_cnt; / / 水平扫描参数的设定 / parameter lineperiod =12'd1040; /行同步周期 parameter h_syncpul

3、se=10'd120; /?型叫藕? parameter h_backporch=10'd61; /行同步后肩 parameter h_activepix=10'd806; /行同步数据有效 / verilog程序 / 垂直扫描参数的设定 / parameter frameperiod=10'd666; parameter v_syncpulse=10'd6; parameter v_backporch=10'd21; parameter v_activepix=10'd604; / / 水平扫描计数x_cnt只负责计数从0计数计到104

4、0 / always (posedge clk or negedge rst_n) if(!rst_n) x_cnt = 1; else if(x_cnt = lineperiod) x_cnt = 1; else x_cnt = x_cnt+ 1; / / 水平扫描信号vsync产生 在0到120时为低电平 / always (posedge clk or negedge rst_n) if(!rst_n) hsync = 1'b1; else if(x_cnt = 1) hsync = 1'b0; /产生hsync信号 else if(x_cnt = h_syncpulse

5、+1) hsync = 1'b1; / / 垂直扫描计数 / always (posedge clk or negedge rst_n) if(!rst_n) y_cnt = 1; else if(y_cnt = frameperiod) y_cnt = 1; else if(x_cnt = lineperiod) y_cnt = y_cnt+1; / / 垂直扫描信号hsync产? verilog程序 / always (posedge clk or negedge rst_n) if(!rst_n) vsync = 1'b1; else if(y_cnt = 1) vsyn

6、c = 1'b0; /产生vsync信号 else if(y_cnt = v_syncpulse+1) vsync = 1'b1; wire valid; /有效显示区标志 assign valid = (x_cnt = (h_syncpulse+h_backporch) (x_cnt (h_syncpulse+h_backporch+h_activepix) (y_cnt = (v_syncpulse+v_backporch) (y_cnt (v_syncpulse+v_backporch+v_activepix); wire9:0 x_pos=x_cnt-h_syncpul

7、se-h_backporch; wire9:0 y_pos=y_cnt-v_syncpulse-v_backporch; /字符的字模 reg7:0 vga_rgb; /* 济(0) 大(1) 济 0x00,0x80, 00800100 0x20,0x40, 20400100 0x17,0xfe, 17fe0100 0x12,0x08, 12080100 0x81,0x10, 81100100 0x40,0xa0, 40a0fefe 0x40,0x40, 40400100 0x11,0xb0, 11b00100 0x16,0x0e, 160e0280 0x21,0x10, 21100280 0

8、xe1,0x10, e1100440 0x21,0x10, 21100440 0x21,0x10, 21108020 0x22,0x10, 22101010 0x22,0x10, 22102021 0x04,0x10, 4010c006 大 0x01,0x00, 0x01,0x00, verilog程序 0x01,0x00, 0x01,0x00, 0x01,0x00, 0xff,0xfe, 0x01,0x00, 0x01,0x00, 0x02,0x80, 0x02,0x80, 0x04,0x40, 0x04,0x40, 0x08,0x20, 0x10,0x10, 0x20,0x08, 0xc0

9、,0x06, */ /此时的数字取模，如是汉字要第一个汉字的第一行加上其次个汉字的第一行。以此类推 parameter line0 = 32'h00800100, line1 = 32'h20400100, line2 = 32'h17fe0100, line3 = 32'h12080100, line4 = 32'h81100100, line5 = 32'h40a0fefe, line6 = 32'h40400100, line7 = 32'h11b00100, line8 = 32'h160e0280, line9

10、= 32'h21100280, linea = 32'he1100440, lineb = 32'h21100440, linec = 32'h21108020, lined = 32'h22101010, linee = 32'h22102021, linef = 32'h4010c006; /显示位数 reg4:0 char_bit; always (posedge clk or negedge rst_n) if(!rst_n) char_bit = 1'h1f; else if(x_pos = 10'd384) c

11、har_bit = 5'd32; /产生vsync信号 else if(x_pos 10'd384 x_pos = 10'd416) char_bit = char_bit - 1'b1; verilog程序 always (posedge clk) if(!valid) vga_rgb = 8'h00; else if(x_pos 10'd384 x_pos = 10'd416) begin case(y_pos) 10'd292: if(line0char_bit) vga_rgb = 8'b111_000_00; e

12、lse vga_rgb = 8'b000_111_00; 10'd293: if(line1char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd294: if(line2char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd295: if(line3char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8

13、9;b000_111_00; 10'd296: if(line4char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd297: if(line5char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd298: if(line6char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10&

14、#39;d299: if(line7char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd300: if(line8char_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd301: if(line9char_bit) vga_rgb = 8'b111_000_00; verilog程序 else vga_rgb = 8'b000_111_00; 10'd302

15、: if(lineachar_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd303: if(linebchar_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd304: if(linecchar_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd305: if(linedchar_bit

16、) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd306: if(lineechar_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; 10'd307: if(linefchar_bit) vga_rgb = 8'b111_000_00; else vga_rgb = 8'b000_111_00; default: vga_rgb = 8'hff; endcase end else vga_rgb = 8'h000_000_11; assign r = vga_rgb7:5; assign g = vga_rgb4:2; assign b = vga_rgb1:0; endmodule 本地地址：e:fpgavediovga_charsrci_vga_char.ucf net cl