基于VHDL的交通灯课程设计论文

1、EDA课程设计 交通灯设计 学院： 电 气 信 息 学 院 专业： 通 信 工 程 班级： 02 学号: 1104140209 姓名： 廖 振 宇 指导教师： 杨 志 芳 2013年11月30日十字路口的信号灯控制电路一、 设计任务与要求1、 实现一个十字路口的信号灯控制电路。2、 信号灯分别由红、黄、绿，左转四个灯组成，运行时，东西方向绿灯亮45秒钟，黄灯亮5秒，左转灯亮15秒，黄灯亮5秒，红灯亮，同时另一方向的绿灯亮，红灯亮的时间为60秒 。期间南北方向绿灯亮40秒，黄灯5秒，左转灯10秒，黄灯5秒。二、 总体框图分频器计数器控制器红绿灯显示显示控制电路扫描显示电路七段数码管 图一交通灯控

2、制系统框图1.设计思路：在某一十字路口交叉地带，可设置东西走向的道路为主道，南北走向的道路为次道，主次车道的交通灯需按交通法则交替运行。则可设计逻辑电路。2.分析系统的逻辑功能： 交通灯控制系统原理图如图一，由计数器、分频器、控制器、分位译码电路、扫描显示电路等部分组成。3.个状态过程如下： 状态一：主干道红灯LED显示数字60，次干道绿灯显示40为状态s0；状态二：次道绿灯主道红灯持续时间小于40s时，s1状态保持不变，若持续时间等于45s时，转换到下一状态。 状态三：次道黄灯计时小于5s主道红灯持续时间小于45s时，s2状态保持不变，若黄灯持续时间等于5s时，s2转换到下一状态。 状态四：

3、次道左转灯主道红灯持续时间小于10s时，s3状态保持不变，若持续时间等于10s时，s3转换到下一状态。状态五：次道黄灯主道红灯持续时间小于5s时，s4=0状态保持不变，若持续时间等于5s时，s4转换到下一状态。状态六：主道绿灯显示数值45，次道红灯显示数值70s，当主道绿灯持续时间小于45s时s5状态保持不变，等于45秒时，s5跳转到下一状态。状态七：主道黄灯显示数值5，次道红灯显示数值25s，当主道黄灯持续时间小于5s时s6状态保持不变，等于5s时，s6跳转到下一状态。状态八：主道左转灯显示数值15，次道红灯显示数值20s，当主道左转灯持续时间小于15s时s7状态保持不变，等于15秒时，s7

4、跳转到下一状态。状态九：主道黄灯显示数值5，次道红灯显示数值5s，当主道黄灯持续时间小于5s时s8状态保持不变，等于5s时，s8跳转到下一状态。三、 选择器件1、 装有Altera公司QuartusII仿真软件的计算机一台。2、 选择FPGA器件：Cyclone中的EP1C12Q240C8。3、 EDA-VI实验箱一台。4、 实现数据下载的数据线，导线。5、 开关以及LED灯。6、 四位八段数码显示管。 四、 功能模块模块一 ：分频器分频器实现的是将高频时钟信号转换成低频时钟信号，clk信号经分频器将50MHz分为250Hz和1Hz提供给计数器、控制器和扫描显示电路所需的时钟计时脉冲。分频器模

5、块（div） VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div isport(clk3:IN std_logic; clkout1,clkout2:OUT std_logic); end div;architecture one of div isbeginprocess(clk3)variable cnt:integer range 0 to 25000000;variable tmp:std_logic;begin if(clk3'event and

6、 clk3='1')then if cnt>=24999999 then cnt:=0; tmp:=not tmp;else cnt:=cnt+1;end if;end if;clkout1<=tmp;end process;process(clk3)variable cnt:integer range 0 to 100000;variable tmp:std_logic;begin if(clk3'event and clk3='1')then if cnt>=99999 then cnt:=0; tmp:=not tmp;else

7、cnt:=cnt+1;end if;end if;clkout2<=tmp;end process; end one;分频器仿真波形模块二： 控制器控制器的作用是根据计数器计数的值控制发光二极管的亮灭。本控制器的设计方法是利用时钟沿的上升沿读取前级计数器的计数值，然后做出反应。主要控制红、绿、黄灯的亮、灭和闪烁。 控制器模块（KZ） VHDL源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY KZ IS PORT(CLK:IN STD_LOGIC; G1,Y1,R1,L1,

8、L2, G2,Y2,R2 :OUT STD_LOGIC);END;ARCHITECTURE ART OF KZ ISBEGIN PROCESS(CLK) IS VARIABLE S:INTEGER RANGE 0 TO 124;BEGINIF(CLK'EVENT AND CLK='1')THEN IF S>124 THEN S:=1; else S:=S+1; IF 0<S AND S<41 THEN 40s内 G1<='0' 主道绿灯亮 Y1<='1' R1<='1' L1<=&

9、#39;1' G2<='1' Y2<='1' R2<='0' 次道红灯亮 L2<='1'ELSIF s=41 THEN 主道绿灯闪烁的第一秒 G1<='1' Y1<='1' R1<='1' L1<='1' G2<='1' Y2<='1' R2<='0' L2<='1'ELSIF s=42 THEN G1<='0&

10、#39; Y1<='1' R1<='1' L1<='1' G2<='1' Y2<='1' R2<='0' L2<='1'ELSIF s=43 THEN G1<='1' Y1<='1' R1<='1' L1<='1' G2<='1' Y2<='1' R2<='0' L2<='1&

11、#39;ELSIF s=44 THEN G1<='0' Y1<='1' R1<='1' L1<='1' G2<='1' Y2<='1' R2<='0' L2<='1'ELSIF s=45 THEN 主道绿灯闪烁最后一秒 G1<='1' Y1<='1' R1<='1' L1<='1' G2<='1' Y2<=

12、'1' R2<='0' L2<='1' ELSIF 45<S AND s<61 THEN G1<='1' Y1<='1' R1<='1' L1<='0' 主道左转灯亮 G2<='1' Y2<='1' R2<='0' L2<='1' ELSIF 60<S AND s<63 THEN G1<='1' Y1<=

13、9;0' 主道黄灯亮 R1<='1' L1<='1' G2<='1' Y2<='1' R2<='0' L2<='1'ELSIF 62<s AND s<103 THEN G1<='1' Y1<='1' R1<='0' 主道红灯亮 L1<='1' G2<='0' 次道绿灯亮 Y2<='1' R2<='1&

14、#39; L2<='1' ELSIF S=103 THEN 次道绿灯闪烁第一秒 G1<='1' Y1<='1' R1<='0' 主道红灯亮 L1<='1' G2<='1' Y2<='1' R2<='1' L2<='1'ELSIF S=104 THEN G1<='1' Y1<='1' R1<='0' L1<='1'

15、 G2<='0' Y2<='1' R2<='1' L2<='1'ELSIF S=105 THEN G1<='1' Y1<='1' R1<='0' L1<='1' G2<='1' Y2<='1' R2<='1' L2<='1'ELSIF S=106 THEN G1<='1' Y1<='1' R

16、1<='0' L1<='1' G2<='0' Y2<='1' R2<='1' L2<='1'ELSIF S=107 THEN 次道绿灯闪烁最后一秒 G1<='1' Y1<='1' R1<='0' L1<='1' G2<='1' Y2<='1' R2<='1' L2<='1'ELSIF 107

17、<s and s<123 THEN G1<='1' Y1<='1' R1<='0' L1<='1' G2<='1' Y2<='1' R2<='1' L2<='0'ELSIF 122<s and s<125 THEN G1<='1' Y1<='1' R1<='0' L1<='1' G2<='1

18、9; Y2<='0' R2<='1' L2<='1' END IF; END IF;END IF; END PROCESS;END; 控制器仿真波形模块三： 显示控制电路输入与计数器相连，输出与扫描显示电路相连VHDL源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XSKZ IS PORT(EN45A,EN45B,EN02A,EN02B,EN15A,EN15B:IN STD_LOGIC; AIN45A,AIN4

19、5B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN15A,AIN15B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN02 :IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY XSKZ;ARCHITECTURE ART OF XSKZ IS BEGIN PROCESS(EN45A,EN45B,EN02A,EN02B,EN15A,EN15B,AIN45A,AIN45B,AIN15A,AIN15B,AIN02)IS B

20、EGIN IF EN45A='0' THEN DOUTM<=AIN45A(7 DOWNTO 0);DOUTB<=AIN45B(7 DOWNTO 0); ELSIF EN45B='0' THEN DOUTM<=AIN45B(7 DOWNTO 0);DOUTB<=AIN45A(7 DOWNTO 0);ELSIF EN02A='0' THEN DOUTM<=AIN02(7 DOWNTO 0);DOUTB<=AIN02(7 DOWNTO 0); ELSIF EN02B='0' THEN DOUTM<

21、;=AIN02(7 DOWNTO 0);DOUTB<=AIN02(7 DOWNTO 0);ELSIF EN15A='0'THEN DOUTM<=AIN15A(7 DOWNTO 0);DOUTB<=AIN15B(7 DOWNTO 0);ELSIF EN15B='0'THEN DOUTM<=AIN15B(7 DOWNTO 0);DOUTB<=AIN15A(7 DOWNTO 0); END IF; END PROCESS;END ARCHITECTURE ART;显示控制仿真波形模块四： 扫描显示电路 扫描显示电路可以根据控制信号，驱动数

22、码管的显示扫描显示模块（SELTIME） VHDL源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY SELTIME ISPORT(CLK2:STD_LOGIC; DOUT1,DOUT2,DOUT3,DOUT4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DAOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO

23、0);END;ARCHITECTURE FUN OF SELTIME ISSIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINSEL<=count;PROCESS(CLK2)BEGINIF(CLK2'EVENT AND CLK2='1')THEN IF(COUNT>="100")THENCOUNT<="000"ELSECOUNT<=COUNT+1;END IF;END IF;CASE COUNT ISWHEN "000"=>DAOUT&l

24、t;=DOUT1;WHEN "001"=>DAOUT<=DOUT2; WHEN "010"=>DAOUT<=DOUT3; WHEN "011"=>DAOUT<=DOUT4;WHEN OTHERS=>DAOUT<="0000"END CASE;END PROCESS;END FUN;扫描显示仿真波形模块五： 45s计数器 该模块的功能是实现绿灯在45s内的倒计时，通过分频器分出来的时钟源clk进行计数。45s模块（CNT45S）VHDL源程序：library ieee;

25、use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CNT45s is port(clk,EN45A,EN45B:in std_logic; DOUT45M,DOUT45B:out std_logic_vector(7 downto 0);end entity CNT45s;architecture art of CNT45s issignal CNT6B:std_logic_vector(5 downto 0);beginprocess(clk,EN45A,EN45B)is begin if(clk'e

26、vent and clk='1')then if EN45A='0'OR EN45B='0' then CNT6B<=CNT6B+1; ELSECNT6B<="000000" end if; end if;end process;process(CNT6B) is begin CASE CNT6B is WHEN"000000"=>DOUT45M<="01000101"DOUT45B<="01100010" WHEN"00000

27、1"=>DOUT45M<="01000100"DOUT45B<="01100001" WHEN"000010"=>DOUT45M<="01000011"DOUT45B<="01100000" WHEN"000011"=>DOUT45M<="01000010"DOUT45B<="01011001"WHEN"000100"=>DOUT45M<=&

28、quot;01000001"DOUT45B<="01011000"WHEN"000101"=>DOUT45M<="01000000"DOUT45B<="01010111"WHEN"000110"=>DOUT45M<="00111001"DOUT45B<="01010110"WHEN"000111"=>DOUT45M<="00111000"DOUT45B&

29、lt;="01010101"WHEN"001000"=>DOUT45M<="00110111"DOUT45B<="01010100"WHEN"001001"=>DOUT45M<="00110110"DOUT45B<="01010011"WHEN"101001"=>DOUT45M<="00000100"DOUT45B<="00100001"WHE

30、N"101010"=>DOUT45M<="00000011"DOUT45B<="00100000"WHEN"101011"=>DOUT45M<="00000010"DOUT45B<="00011001"WHEN"101100"=>DOUT45M<="00000001"DOUT45B<="00011000"WHEN OTHERS=>DOUT45M<=&q

31、uot;00000000"DOUT45B<="00000000"END CASE;END PROCESS;END ARCHITECTURE ART; 45秒计数器仿真波形模块六：15s计数器 主要控制左转灯L1、L2的倒计时功能，控制他们的15s倒计时。15s模块（CNT15S）VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CNT15s is port(clk,EN15A,EN15B:in std_logic; DOUT15M,D

32、OUT15B:out std_logic_vector(7 downto 0);end entity CNT15s;architecture art of CNT15s issignal CNT6B:std_logic_vector(3 downto 0);beginprocess(clk,EN15A,EN15B)is begin if(clk'event and clk='1')then if EN15A='0'OR EN15B='0' then CNT6B<=CNT6B+1; ELSECNT6B<="0000&q

33、uot; end if; end if;end process;process(CNT6B) is begin CASE CNT6B is WHEN"0000"=>DOUT15M<="00010110"DOUT15B<="00011000"WHEN"0001"=>DOUT15M<="00010101"DOUT15B<="00010111" WHEN"0010"=>DOUT15M<="00010100

34、"DOUT15B<="00010110"WHEN"0011"=>DOUT15M<="00010011"DOUT15B<="00010101"WHEN"0100"=>DOUT15M<="00010010"DOUT15B<="00010100"WHEN"0101"=>DOUT15M<="00010001"DOUT15B<="00010011&

35、quot;WHEN"0110"=>DOUT15M<="00010000"DOUT15B<="00010010"WHEN"0111"=>DOUT15M<="00001001"DOUT15B<="00010001"WHEN"1000"=>DOUT15M<="00001000"DOUT15B<="00010000"WHEN"1001"=>DOU

36、T15M<="00000111"DOUT15B<="00001001"WHEN"1010"=>DOUT15M<="00000110"DOUT15B<="00001000"WHEN"1011"=>DOUT15M<="00000101"DOUT15B<="00000111"WHEN"1100"=>DOUT15M<="00000100"DOUT

37、15B<="00000110"WHEN"1101"=>DOUT15M<="00000011"DOUT15B<="00000101"WHEN"1110"=>DOUT15M<="00000010"DOUT15B<="00000100"WHEN"1111"=>DOUT15M<="00000001"DOUT15B<="00000011"WHEN

38、OTHERS=>DOUT15M<="00000000"DOUT15B<="00000000"END CASE;END PROCESS;END ARCHITECTURE ART;15秒计数器仿真波形模块七：2s计数器 控制黄灯Y1、Y2的2s倒计时功能2s模块（CNT2S）VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CNT02s is port(clk,EN02A,EN02B:in std_logic; DO

39、UT02M:out std_logic_vector(7 downto 0);end entity CNT02s;architecture art of CNT02s issignal CNT2B:std_logic_vector(1 downto 0);beginprocess(clk,EN02A,EN02B)is begin if(clk'event and clk='1')then if EN02A='0'OR EN02B='0' then CNT2B<=CNT2B+1; ELSECNT2B<="00"

40、; end if; end if;end process;process(CNT2B) is begin CASE CNT2B is WHEN"00"=>DOUT02M<="00000010"WHEN"01"=>DOUT02M<="00000001" WHEN OTHERS=>DOUT02M<="00000000"END CASE;END PROCESS;END ARCHITECTURE ART;2秒计数器仿真波形模块八：译码器（decode3_8）3-8译码

41、器模块VHDL源程序：LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY decode3_8 IS PORT(SEL:IN std_logic_vector(2 downto 0); Q:OUT std_logic_vector(7 downto 0);END decode3_8;ARCHITECTURE a OF decode3_8 ISBEGIN Q<="11111110"when sel=0 else "11111101"when sel=1 else "11111011"when sel=2 else "11110111"when sel=3 else "11111111"END a;模块九：数码显示器（deled）数码显示模块VHDL源程序：LIBRARY ieee;use iee