CoreDuorchitecture 國立清華大學酷睿架构國立清華大學

1、copyright 2006, intel corporation. all rights reserved. *other brands and names are the property of their respective ownersintel core duo processor architecturecopyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporatio

2、n or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.2objectivelearn about capabilities of intel core duo processor for multi-threading vector/simd floating point execution cache architecture power managementcopyright 2006

3、, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.3motivations for new architectureintels fir

4、st low power dual core cpunew design philosophy of performance per wattenabling new usage models for mobile and desktop platforms65nm manufacturing technologycopyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation

5、or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.4key features intel core duo processor dual execution cores out-of-order execution engine 32kb l1 instruction and 32kb l1 data caches, 2mb l2 cache 667 mhz system bus with

6、 5333mb/s bandwidth intel smart cache intel enhanced speedstep technology intel dynamic power coordination intel digital media boostcopyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the

7、 united states or other countries. *other brands and names are the property of their respective owners.5resource utilizationnote: each box represents a processor execution unittime (proc. cycles)superscalardual corehyper-threadingcopyright 2006, intel corporation. all rights reserved. intel and the

8、intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.6key featuresdual core two physical cores in a package each with its own execution resources each w

9、ith its own l1 cache 32k instruction and 32k data 8-way set associative; 64-byte line both cores share the l2 cache 2mb 8-way set associative; 64-byte line size 10 clock cycles latency; write back update policy exe corefp unitexe corefp unitl2 cachel1 cachel1 cachesystem bus (667mhz, 5333mb/s)copyri

10、ght 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.7key features intel smart cache sha

11、red between the two cores advanced transfer cache architecture reduced bus traffic both cores have full access to the entire cache dynamic cache sizingcopyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its

12、subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.8key featuresenhanced intel speedstep technologymulti-point demand-based switchingsupports transitions to deeper sleep modesclock partitioning and recoverydynamic bus parkingcopy

13、right 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the property of their respective owners.9key featuresintel digital media

14、booststreaming simd streaming simd extensions (sse) decoder extensions (sse) decoder throughput improvementthroughput improvementsse/sse2 sse/sse2 instruction instruction optimizationoptimizationfloating point floating point performance performance enhancementenhancementnew enhanced new enhanced str

15、eaming simd streaming simd extensions 3 (sse3)extensions 3 (sse3)copyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the

16、property of their respective owners.10simd fp using aos format*thread synchronizationvideo encodingcomplex arithmeticfp to integer conversionshaddpd, hsubpdhaddps, hsubpsmonitor, mwaitlddquaddsubpd, addsubps,movddup, movshdup,movsldupfisttp* also benefits complex arithmetic and vectorizationkey feat

17、uresintel digital media boost sse3 instructionscopyright 2006, intel corporation. all rights reserved. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states or other countries. *other brands and names are the property of their

18、respective owners.11summary intel core duo processor is at the core of intel desktop and mobile platforms (2ghz, 5333mb/s bandwidth, 31w) dual core enables true multi-threaded execution intel smart cache enables greater system responsiveness intel speedstep technology provides very low system down times intel dynamic power management improves performance and battery life intel digital media boost delivers a rich mult