数电实验数字钟上机报告华科

1、max+plus ii多功能数字钟设计 自动化1001班 刘杰 学号 u200914402多功能数字钟设计一、实验目的1. 掌握可编程逻辑器件的应用开发技术设计输入、编译、仿真和器件编程；2. 熟悉一种eda软件使用；3. 掌握verilog设计方法；二、实验任务1. 已知条件max+plus ii软件fpga实验开发装置(该装置可以提供3路时钟信号和译码显示电路）基本功能具有“秒”、“分”、“时”计时功能，小时按24小时制计时。具有校时功能，能对“分”和“小时”进行调整2. 扩展功能仿广播电台正点报时。在59分51秒、53秒、55秒、57秒、59秒发出音响结束时刻为整点。 定时控制，其时间自

2、定；3. 选做内容任意时刻闹钟自动报整点时数小时计数器改为12翻13、 数字钟设计分析-功能框图4、 设计编译 1. 设计输入module top_clock (second,ap,cp,ncr,en,adj_min,adj_hour,ctrlbell,sethrkey,setminkey,alarm,_1khz,_500hz,rhr,rmin); input cp,ncr,en,adj_min,adj_hour,ctrlbell,_1khz,_500hz,sethrkey,setminkey; output7:0 rhr,rmin,second; output alarm; wire7:0

3、set_hr,set_min,hour,minute; wire alarm_clock,alarm_r,alarm_r1; wire _1khz,_500hz,cp; output ap; reg7:0 rhr,rmin,second; supply1 vdd; wire minl_en,minh_en,hour_en,ap; wire hrh_equ,hrl_equ,minh_equ,minl_equ; wire time_equ; /hour:minute:second counter counter10 u1(second3:0,ncr,en,cp); counter6 u2(seco

4、nd7:4,ncr,(second3:0=4'h9),cp); assign minl_en=adj_min?vdd:(second=8'h59); assign minh_en=(adj_min&&(minute3:0=4'h9)|(minute3:0=4'h9)&&(second=8'h59); counter10 u3(minute3:0,ncr,minl_en,cp); counter6 u4(minute7:4,ncr,minh_en,cp); assign hour_en=adj_hour?vdd:(minut

5、e=8'h59)&&(second=8'h59); counter24 u5(hour7:4,hour3:0,ncr,hour_en,cp,ap);/若闹钟调整使能端开启，数码管显示闹铃设置时间，反之显示时钟时间。 /*always (setminkey or sethrkey) case(setminkey,sethrkey)2'b11:begin rmin7:0=set_min7:0;rhr7:0=set_hr7:0; end2'b10:begin rmin7:0=set_min7:0;rhr7:0=hour7:0;end2'b01:

6、begin rmin7:0=minute7:0;rhr7:0=set_hr7:0;end2'b00:begin rmin7:0=minute7:0;rhr7:0=hour7:0;end endcase*/ /选择类型1always (posedge cp) if(setminkey) rmin7:0=set_min7:0; else rmin7:0=minute7:0; always (posedge cp) if (sethrkey) rhr7:0=set_hr7:0; else rhr7:0=hour7:0;/或者选择类型2counter10 uc0(set_min3:0,vdd,

7、setminkey,cp); counter6 uc1(set_min7:4,vdd,(set_min3:0=4'h9),cp);counter24 su2(set_hr7:4,set_hr3:0,vdd,sethrkey,cp,ap);/comparate the set timecomparator su4(hrh_equ,set_hr7:4,hour7:4);comparator su5(hrl_equ,set_hr3:0,hour3:0);comparator su6(minh_equ,set_min7:4,minute7:4);comparator su7(minl_equ,

8、set_min3:0,minute3:0);assign time_equ=(hrh_equ && hrl_equ && minh_equ && minl_equ);assign alarm_clock=ctrlbell?(time_equ&&_500hz):1'b0; ring u7(alarm_r,minute,second,_1khz,_500hz);/仿广播电台正点报时 ring1 u8(alarm_r1,minute,hour,second,_500hz);/自动报整点时数assign alarm=alarm_r

9、|alarm_r1|alarm_clock ; /将闹钟、报时全部归于扬声器输出端endmodulemodule counter10(q,ncr,en,cp); input cp,ncr,en; output3:0q; reg 3:0 q; always(posedge cp or negedge ncr) begin if(ncr)q<=4'b0000; else if(en) q<=q; else if(q=4'b1001)q<= 4'b0000; else q<=q+1'b1; endendmodulemodule counter6

10、(q,ncr,en,cp); input cp,ncr,en; output3:0q; reg 3:0q;always (posedge cp or negedge ncr) begin if(ncr) q<=4'b0000; else if(en) q<=q; else if(q=4'b0101) q<=4'b0000; else q<=q+1'b1; endendmodule module counter24(cnth,cntl,ncr,en,cp,ap); input cp,ncr,en; output3:0cnth,cntl; o

11、utput ap;reg 3:0cnth,cntl;reg ap; reg co;always(posedge cp or negedge ncr)begin if(ncr) begin cnth,cntl<=8'b00010010; ap<=1'b0;end else if(en)begin cnth,cntl<=cnth,cntl;ap<=ap;end else if(cnth>1)|(cntl>9)|(cnth=1)&&(cntl>=2) begin cnth<=4'b0000; cntl<=4

12、'b0001;ap<=(ap); end else if(cnth=1)&&(cntl<2) begin cnth<=cnth; cntl<=cntl+1'b1;end else if(cntl=9) begin cnth<=cnth+1'b1; cntl<=4'b0000;end else begin cnth<=cnth; cntl<=cntl+1'b1;endendendmodulemodule comparator(equ,a,b);input 3:0a,b;output equ;a

13、ssign equ=(a=b);endmodule/电台报时module ring(alarm_r,minute,second,_1khz,_500hz);input _1khz,_500hz;wire _1khz,_500hz;input 7:0minute,second;output alarm_r;reg alarm_r;always (minute or second)if(minute=8'h59)case(second)8'h51:alarm_r=_500hz;8'h53:alarm_r=_500hz;8'h55:alarm_r=_500hz;8&#

14、39;h57:alarm_r=_500hz;8'h59:alarm_r=_1khz;default:alarm_r=1'b0;endcaseelse alarm_r=1'b0;endmodule/整点报时module ring1(alarm_r1,minute,hour,second,_500hz);input _500hz;wire _500hz;input 7:0minute,second,hour;output alarm_r1;reg alarm_r1;always (hour or minute or second)if(minute=8'h00)as

15、sign alarm_r1=(second=8'h01)|(second=8'h03)|(second=8'h05)|(second=8'h07)|(second=8'h09)|(second=8'h11)|(second=8'h13)|(second=8'h15)|(second=8'h17)|(second=8'h19)|(second=8'h21)|(second=8'h23)&&_500hz&&(second<(hour*2);endmodule 2. 电路仿真图为起始设置闹钟，由图可得出闹铃设为1h1min处, 并能观察出电路仿真自动报整点时数.在设置闹铃后，可分辨观察到仿广播电台正点报时、自动报整点时数5 实验心得1. 该课程设计所设计的各种模块和原理与数字电子技术的理论