电子设计自动化EDA课程设计电子钟设计

1、电子设计自动化eda课程设计题目 电 子 钟 设 计 专业 电子信息科学与技术 班级 电子一班 学号 20104672 姓名 目录一、实验目的-（1）二、实验内容-（1）三、工作原理-（1）四、vhdl源程序代码-（2） 1、 分频模块-（2）2、走时、校时模块-（4）3、闹钟模块-（7）4、秒表模块-（9）5、功能控制模块-（13）6、选择输出模块-（14）7、数码管显示、亮度可调模块-（15）8、总体例化-（17）五、心得体会-（18）一 . 实验目的 练习综合设计能力，熟练应用quartursii软件，熟练掌握课本知识，设计一个数字钟，以提高自己的动手能力二. 实验内容 基本功能要求 设

2、计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。 扩展功能要求 秒表功能，闹钟功能，调整数码管亮度 试验箱设置1、 选择模式7；2、 数码管8左边的跳线选择close;三. 工作原理 数字钟模块分化如下： 分频模块功能控制模块走时/调时选择输出显示数码管显示、亮度可调闹钟选时定时比较秒表 （1） 分频模块可分出1hz、100 hz 、1000hz、5000 hz，分别用于正常走时、秒表、定时比较和数码管扫描。 （2） 功能控制模块由一个简单加法器实现看，用键7控制，当按一下键7，来一个单脉冲，加法器内部定义信号循环自加实现模式转换，不断控制各功能模块的使能键，实现功能转换。 （3）

3、走时/调时模块通过使能端选择不同输入时钟，切换两个模式，当en=1时，可以调时，键4为位选键，键1为加数键，en=0时，正常走时。只有在调时时，走时停止，在其他功能时走时正常进行。此模块由时、分、秒三部分组成。 （4） 闹钟模块由两部分组成，闹钟选时和定时比较，选定闹钟时间后，在1000 hz的驱动下，比较器时刻与正常走时输出比较，当两时间相等时，比较器输出以时钟信号使蜂鸣器发出响声。 （5）秒表模块由计数器实现，键1为清零键，当百分之一秒计满一百进一位，秒计满六十进一位。可显示分、秒、百分之一秒。 （6）选择输出显示模块 ，由一个加法器实现 ，此模块与功能控制模块为同一驱动，选择输出当前功能

4、的输出。（7）数码管显示、亮度可调模块由5000hz驱动，显示部分分为段选与位选。键7控制选择到亮度调节功能，键1实现亮度调节。四. 各模块vhdl源代码1、分频模块 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div is -分频port(clk:in std_logic; clk1,clk100,clk1000,clk1m:out std_logic); end;architecture one of div issignal clk1_tmp:std_logic;signa

5、l clk2_tmp:std_logic;signal clk3_tmp:std_logic;signal clk4_tmp:std_logic;signal cnt1:integer range 0 to 4999999; - 1hz 正常走时signal cnt100:integer range 0 to 49999; -100hz 秒表驱动signal cnt1000:integer range 0 to 4999 ; -1000 扫描闹钟比较器signal cnt1m:integer range 0 to 999; -5000 扫描频率beginp1: process(clk) beg

6、in if clk'event and clk='1' then if cnt1<4999999 then cnt1<=cnt1+1; elsecnt1<=0; clk1_tmp<=not clk1_tmp ;end if;end if;end process;p2: process(clk) begin if clk'event and clk='1' then if cnt100<49999 then cnt100<=cnt100+1; elsecnt100<=0; clk2_tmp<=not

7、clk2_tmp ;end if;end if;end process;p3: process(clk) begin if clk'event and clk='1' then if cnt1000<4999 then cnt1000<=cnt1000+1; elsecnt1000<=0; clk3_tmp<=not clk3_tmp ;end if;end if;end process;p4: process(clk) begin if clk'event and clk='1' then if cnt1m<999

8、 then cnt1m<=cnt1m+1; elsecnt1m<=0; clk4_tmp<=not clk4_tmp ;end if;end if;end process;clk1<=clk1_tmp;clk100<=clk2_tmp;clk1000<=clk3_tmp;clk1m<=clk4_tmp;end;2、走时、调时模块（1） 秒走时模块use ieee.std_logic_1164.all; library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;en

9、tity scnt60 is -秒计时，调时，60进制。port (clk,en:in std_logic; cq : out std_logic_vector(7 downto 0); -3-0 个位 7-4 十位 两位输出 cout:out std_logic); -进位end entity scnt60;architecture behv of scnt60 issignalc1,c2 : std_logic_vector (3 downto 0):= (others=>'0'); begin process(clk) begin if clk'event

10、and clk='1' then if en ='0' then if c1<9 then c1<=c1+1; else c1<=(others=>'0'); if c2<5 then c2<=c2+1; else c2<=(others=>'0'); end if; end if; end if; end if; if c1=9 and c2=5 then cout <='1'-进位 else cout <='0' end if; cq(

11、3 downto 0)<=c1; cq(7 downto 4)<=c2; end process;end architecture;（2）分走时、调时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity mscnt60 is -分计时，调时，60进制。port (clkin,en,adjust1,add:in std_logic; cq : out std_logic_vector(7 downto 0) -3-0 个位

12、 7-4 十位 两位输出 cout:out std_logic); -进位end entity mscnt60;architecture behv of mscnt60 issignalc1,c2 : std_logic_vector (3 downto 0):= (others=>'0');signal clk:std_logic; begin p1:process(en) -选择计时或调时信号 begin if en='1' then clk<=(add and adjust1); else clk<=clkin; end if; end

13、process; p2: process(clk) begin if clk'event and clk='1' then -简单计数器 if c1<9 then c1<=c1+1; else c1<=(others=>'0'); if c2<5 then c2<=c2+1; else c2<=(others=>'0'); end if; end if; end if; if c1=9 and c2=5 then cout <='1'-进位 else cout <

14、='0' end if; cq(3 downto 0)<=c1; cq(7 downto 4)<=c2; end process;end architecture;（3）时走时、调时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity hcnt24 is -时计时 24进制port (clkin,en,adjust2,add:in std_logic; cq : out std_logic_vector(

15、7 downto 0); -0-3是个位，4-7是十位 end entity hcnt24 ;architecture behv of hcnt24 issignalc1,c2 : std_logic_vector (3 downto 0):= (others=>'0');signal clk:std_logic; begin p1:process(en) -选择计时与调时信号 begin if en='1' then clk<=(add and adjust2); else clk<=clkin; end if; end process; p

16、2: process(clk) -简单计数器 begin if clk'event and clk='1' then if c1<9 and c2<2 then c1<=c1+1; elsif c1=9 and c2<2 then c2<=c2+1;c1<="0000" elsif c2=2 and c1<3 then c1<=c1+1; else c1<="0000"c2<="0000" end if; end if; cq(3 downto 0)&

17、lt;=c1; cq(7 downto 4)<=c2; end process;end architecture;（4）控制时、分位切换程序 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adjust is -控制时位与分位 port (choice:in std_logic; adjust1:out std_logic; adjust2:out std_logic); end entity; architecture one of adjust is signal sel:

18、 std_logic_vector(1 downto 0); begin p1: process(choice) begin if choice'event and choice='1' then - 位选信号 if sel<1 then sel<=sel+1; else sel<="00" end if; end if; end process; p2:process(sel,choice) -切换时位与分位 begin case sel is when "00" => adjust1<='

19、1'adjust2<='0' when "01" => adjust2<='1'adjust1<='0' when others=>adjust2<='0'adjust1<='0' end case ; end process; end one ; （5）例化语句library ieee;use ieee.std_logic_1164.all; entity lihua is - 走时与调时例化 port (select1 :in std_log

20、ic; -键4 clk,add, en :in std_logic; - add键7 mput,sput,hput:out std_logic_vector(7 downto 0) ); end lihua; architecture one of lihua is component scnt60 port (clk,en:in std_logic; cq : out std_logic_vector(7 downto 0); cout:out std_logic); end component; component mscnt60 port (clkin,en,adjust1,add:in

21、 std_logic; cq : out std_logic_vector(7 downto 0); cout:out std_logic); end component; component hcnt24 is port (clkin,en,adjust2,add:in std_logic; cq : out std_logic_vector(7 downto 0); end component ; component adjust is port (choice:in std_logic; adjust1:out std_logic; adjust2:out std_logic); end

22、 component; signal a,b,c,d,e:std_logic; begin u0: scnt60 port map(clk=>clk,en=>en,cq=>sput,cout=>a); u1: mscnt60 port map(clkin =>a,en=>en,add=>add,adjust1=>c,cq=>mput,cout=>b); u2: hcnt24 port map (clkin=>b,en=>en,add=>add,adjust2=>d,cq=>hput); u3: adjus

23、t port map (choice=>select1,adjust1=>c,adjust2=>d);end one;end one ; 3、闹钟模块（1）闹钟选时模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;-闹钟选时entity xuanshi is port (add,select2,en:in std_logic; -select2选位 m_clk,h_clk,s_clk:out std_logic_vector(7 downto 0); end xuanshi;

24、architecture one of xuanshi is signal mc1,mc2,hc1,hc2:std_logic_vector(3 downto 0); signal xuanwei :integer range 0 to 1; begin p1: process(add) begin if en='1' then if add'event and add='1' then -分位 if xuanwei=0 then if mc1<9 then mc1<=mc1+1; else mc1<="0000"

25、if mc2<5 then mc2<=mc2+1; else mc2<="0000" end if; end if; elsif xuanwei=1 then -时位 if hc1<9 and hc2<2 then hc1<=hc1+1; elsif hc1=9 and hc2<2 then hc2<=hc2+1 ;hc1<="0000" elsif hc1<3 and hc2=2 then hc1<=hc1+1;hc2<="0000" else hc1<=

26、"0000"hc2<="0000" end if; end if; end if; end if; s_clk<="00000000" -调闹钟时，秒输出为零 m_clk(3 downto 0)<=mc1; m_clk(7 downto 4)<=mc2; h_clk(7 downto 4)<=hc2; h_clk(3 downto 0)<=hc1; end process; p2: process(select2) begin if select2'event and select2=

27、9;1' then if xuanwei <1 then xuanwei <=xuanwei+1; else xuanwei<=0; end if; end if; end process; end architecture;（2）闹钟定时比较器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dingshi is -闹钟定时响 port(h_clk,h_ala,m_ala,m_clk:in std_logic_vector(7 downto 0); clk:

28、in std_logic; -1000hz,用于检测记时 al_out:out std_logic); -使蜂鸣器响的时钟end entity;architecture one of dingshi issignal a:std_logic_vector(7 downto 0 );signal b:std_logic;begin process(h_clk,h_ala,m_clk,m_ala,clk) begin if clk'event and clk='1' then if h_clk=h_ala and m_clk=m_ala then - 循环自减以实现输出时钟

29、信号 a<="11111111" ; end if; if a>"00000000" then a<=a-1; b <=not b; if b='1'then al_out<='1' else al_out<='0' end if; end if ; end if; end process;end one;4、秒表模块（1）百分之一秒走时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned

30、.all; entity run_s is -跑百分之一秒 port(clk,rst,en:in std_logic; m_out : out std_logic_vector(7 downto 0); ms_jw:out std_logic); end entity; architecture one of run_s is signal ms_c1,ms_c2 :std_logic_vector(3 downto 0); begin process(rst,clk) begin if rst='1' then ms_c1<="0000"ms_c2&

31、lt;="0000" -清零 elsif en='1' then if clk'event and clk='1' then if ms_c1<9 then ms_c1<=ms_c1+1; else ms_c1<=(others=>'0'); if ms_c2<9 then ms_c2<=ms_c2+1; else ms_c2<=(others=>'0'); end if ; end if; end if ; end if; if ms_c1=9 and

32、ms_c2=9 then ms_jw <='1'-进位 else ms_jw <='0' end if; m_out(7 downto 4)<=ms_c2; m_out (3 downto 0)<=ms_c1; end process; end one ;（2）秒走时 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity run_ss is -跑秒 port (clk,rst,en:in std_logic; s_out :out s

33、td_logic_vector(7 downto 0); s_jw:out std_logic); -进位 end entity; architecture one of run_ss is signal s_c1,s_c2:std_logic_vector(3 downto 0); begin process(clk) begin if rst='1' then s_c1<="0000"s_c2<="0000" -清零 elsif en='1' then if clk'event and clk=&#

34、39;1' then if s_c1<9 then s_c1<=s_c1+1; else s_c1<=(others=>'0'); if s_c2<5 then s_c2<=s_c2+1; else s_c2<=(others=>'0'); end if; end if; end if; end if; if s_c1=9 and s_c2=5 then s_jw <='1'-进位 else s_jw <='0' end if; s_out(3 downto 0)

35、<=s_c1 ; s_out(7 downto 4 )<=s_c2; end process; end architecture; （3）分走时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity run_m is -跑分 port (clk,rst,en:in std_logic; s_out :out std_logic_vector(7 downto 0); end entity; architecture one of run_m is signal s_c1,s_c2

36、:std_logic_vector(3 downto 0); begin process(clk) begin if rst='1' then s_c1<="0000"s_c2<="0000" -清零 elsif en ='1' then if clk'event and clk='1' then if s_c1<9 then s_c1<=s_c1+1; else s_c1<=(others=>'0'); if s_c2<5 then s_c

37、2<=s_c2+1; else s_c2<=(others=>'0'); end if; end if; end if; end if; s_out(3 downto 0)<=s_c1 ; s_out(7 downto 4 )<=s_c2; end process; end architecture; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity xiao is -用加法器实现脉冲转换为电平 port (stop:in std_log

38、ic; rst:out std_logic); -控制调零 end entity; architecture one of xiao is signal model :std_logic_vector(1 downto 0); begin p1 :process(model) begin if model=1 then rst<='1' elsif model=0 then rst<='0' end if; end process; p2:process(stop) begin if stop'event and stop='1

39、9; then if model<1 then model<=model+1; else model<="00" end if; end if; end process; end architecture; （4）转换电平控制为脉冲控制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity xiao is -用加法器实现脉冲转换为电平 port (stop:in std_logic; rst:out std_logic); -控制调零 end enti

40、ty; architecture one of xiao is signal model :std_logic_vector(1 downto 0); begin p1 :process(model) begin if model=1 then rst<='1' elsif model=0 then rst<='0' end if; end process; p2:process(stop) begin if stop'event and stop='1' then if model<1 then model<=m

41、odel+1; else model<="00" end if; end if; end process; end architecture; （5）例化语句library ieee;use ieee.std_logic_1164.all;entity lihua_p is -例化秒表 port (clk,rst,en:in std_logic; mput,sput,ssput:out std_logic_vector(7 downto 0) );-毫秒，秒，分输出end entity; architecture one of lihua_p is component

42、 run_s is port(clk,rst,en:in std_logic; m_out : out std_logic_vector(7 downto 0); ms_jw:out std_logic); end component; component run_ss is port (clk,rst,en:in std_logic; s_out :out std_logic_vector(7 downto 0); s_jw:out std_logic); end component; component run_m is port (clk,rst,en:in std_logic; s_o

43、ut :out std_logic_vector(7 downto 0);end component;signal a,b:std_logic; begin u0: run_s port map (clk=>clk,rst=>rst,m_out=>ssput,ms_jw=>a,en=>en); u1: run_ss port map (clk=>a,rst=>rst,s_out=>sput,s_jw=>b,en=>en); u2: run_m port map (clk=>b,rst=>rst,s_out=>mput,en=>en);end;5、功能控制模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity option is -功能模块选择 port(ch