各种触发器的VHDL程序.doc

1、题目：写出带异步复位边沿（下降沿）JK 触发器的VHDL程序：LIBRARY IEEE;USEENTITY jk1isPORT (clk,R,S : INSTD_LOGIC;j,k: INSTD_LOGIC;q,qn : OUTSTD_LOGIC);END jk1;ARCHITECTURE one OF jk1 ISSIGNAL q_s : STD_LOGIC;BEGINPROCESS (R,S,clk,j,k)BEGINIF (R=1 AND S=0) THENq_s=0;ELSIF(R=0 AND S=1) THENq_s=1;ELSIF clkEVENT AND clk=0 THENIF

2、 (J=0 AND k=0) THENq_s= q_s;ELSIF (J=0 AND k=1)THENq_s=0;ELSIF (J=1 AND k=0)THENq_s=1;ELSIF (J=1 AND k=1) THENq_s=NOT q_s;END IF;END IF;END PROCESS;q=q_s;qn=not q_s;END one;基本 RS触发器entity rsff isport(r,s:in std_logic;q,qb:out std_logic);end rsff;architecture rtl of rsff issignal q_temp,qb_temp:std_l

3、ogic;beginprocess(r,s)beginif(s=1 and r=0)thenq_temp=1;qb_temp=0;elsif(s=0 and r=1)thenq_temp=0;qb_temp=1;elseq_temp=q_temp;qb_temp=qb_temp;end if;end process;q=q_temp;qb=qb_temp;end rtl;.同步 RS触发器library ieee;use synrsff isport(clk,r,s:in std_logic;q,qb:out std_logic);end synrsff;architecture rtl of

4、 synrsff issignal q_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(clk=1)thenif(s=1 and r=0)thenq_temp=1;qb_temp=0;elsif(s=0 and r=1)thenq_temp=0;qb_temp=1;elseq_temp=q_temp;qb_temp=qb_temp;end if;elseq_temp=q_temp;qb_temp=qb_temp;end if;end process;q=q_temp;qb=qb_temp;end rtl;.同步 D触发器library i

5、eee;use synd isport(clk,d:in std_logic;q,qb:out std_logic);end synd;architecture rtl of synd issignal q_temp,qb_temp:std_logic;beginprocess(clk)beginif(clk=1)thenq_temp=d;qb_temp=not d;elseq_temp=q_temp;qb_temp=qb_temp;end if;end process;q=q_temp;qb=qb_temp;end rtl;带异步置位复位边沿（上升沿）D 触发器library ieee;use adff isport(clk,d,r,s:in std_logic;q,qb:out std_logic);end adff;architecture rtl of adff issignal q_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(r=0 and s=1)thenq_temp=1;qb_temp=0;elsif(r=1 and s=0)thenq_temp=0;qb_temp=1;elsif(cl