电子技术基础数字部分

1、4.6.1module_2to4decoder(a1,a0,e,y);input a,b,e;output 3:0y;wire a1not,a0not,enot;not n1(a1not,a1), n2(a0not,a0), n3(enot,e);nand n4(y0,a1not,a0not,enot),n5(y1,a1not,a0,enot),n6(y2,a1,a0not,enot),n7(y3,a1,a0,enot);endmodule4.6.2module_2to1muxtri(a,b,sel,l);input a,b,sel; output l; tri l; bufif1(l,b,s

2、el); bufif0(l,a,sel);endmodule4.6.3module halfadder(s,c,a,b); input a,b; output s,c;xor(s,a,b); and(c,a,b);endmodulemodule fulladder(s,co,a,b,ci); input a,b,ci; output s,co; wire s1,d1,d2;halfadder ha1(s1,d1,a,b); halfadder ha2(s,d2,s1,ci); or g1(co,d2,d1);endmodulemodule_4bit_adder(s,c3,a,b,c_1); i

3、nput3:0a,b; input c_1; output 3:0s; output 3:0c3; wire c0,c1,c2;fulladder fa0(s0,c0,a0,b0,c_1), fa1(s1,c1,a1,b1,c0), fa2(s2,c2,a2,b2,c1), fa3(s3,c3,a3,b3,c2);endmodule4.6.4module decoder_df(a1,a0,e,y); input a1,a0,e; output3:0y;assigny0=(a1&a0&e);assigny1=(a1&a0&e);assigny2=(a1&a0&e);assigny3=(a1&a0

4、&e);endmodule4.6.5module binary_adder(a,b,cin,sum,cout); input 3:0a,b; input cin; output 3:0sum; output cout; assign cout,sum=a+b+cin;endmodule4.6.6module mux2x1_df(a,b,sel,l); input a,b,sel; output l; assign l=sel?a:b;endmodule4.6.7module mux2to1_bh(a,b,sel,l); input a,b,sel; output l; reg l; alway

5、s (sel or a or b) if(sel=1) l=b; else l=a;endmodule4.6.8module mux4to1_bh(a ,sel,e,l);input3:0a;input1:0sel;output l;reg l;always (a or sel or e) begin if(e=1) l=0;else case(sel) 2 d0 :l=a0; 2 d1 :l=a1; 2 d2 :l=a2; 2 d3 :l=a3; endcase endendmodule5.5.1module d_lanch(q,d,e); output q; input d,e;reg q

6、;always (e or d) if(e) q=d;endmodule5.5.2module dff(q,d,cp);output q; input d,cp; reg q;always (posedge cp) q=d;endmodulemodule async_set_rst_dff(q,qn,d,cp,sd,rd);output q,qn;input d,cp,sd,rd; reg q,qn;always (posedge cp or negedge sd or negedge rd )if(sd|rd)if(sd) begin q=1 b1; qn=1 b0; end else be

7、gin q=1 b0; qn=1 b1; endelse begin q=d; qn=d; endendmodulemodule sync _rst_dff(q ,d,cp,rd); output q; input d,cp,rd; reg q; always (posedge cp) if(rd)q=1 b0; else q=d;endmodule5.5.3module jk_ff(q,qnot,j,k,cp); output q,qnot; input j,k,cp; reg q; assign qnot=q; always (negedge cp ) case (j,k) 2b00:q=

8、q;2b01:q=1b0;2b10:q=1b1;2b11:q=q; endcaseendmodule6.6.1module shift74x194(s1,s0,d,dsl,dsr,q,cp,cr); input s1,s0; input dsl,dsr; input cp,cr;input 3:0d;output 3:0q;reg 3:0q;always (posedge cp or negedge cr) if(cr)q=4b0000; else case(s1,s0) 2b00:q=q; 2b01:q=q2:0,dsr; 2b10:q=dsl ,q3:1 ; 2b11:q=d; endca

9、seendmodule6.6.2module counter74x161(cep,cet,pe,d,cp,cr,q,tc); input cep,cet,pe,d,cp,cr; input 3:0d; output tc; output 3:0q; reg 3:0q; wire ce;assign ce= cep&cet;assign tc=cet&(q=4b1111);always (posedge cp or negedge cr) if(cr)q=4b0000; else if(pe)q=d; else if(ce)q=q; else q=q+1b1;endmodule6.6.3modu

10、le ripplecounter (q0,q1,q2,q3,cp,cr);output q0,q1,q2,q3;input cp,cr;d_ff ff0(q0,q0,cp,cr);d_ff ff1(q1,q1,q0,cr);d_ff ff2(q2,q2,q1,cr);d_ff ff3(q3,q3,q2,cr);endmodulemodule d_ff(q,d,cp,rd); output q; input d,cp,rd; reg q;always (negedge cp or negedge rd) if(rd)q=1b0;elseq=d;endmodule6.6.4module m10_c

11、ounter(ce,cp,cr,q); input ce,cp,cr;output 3:0q;reg 3:0q;always (posedge cp or negedge cr) if(cr)q=4b1001) q=4b0000; else q=q+1b1;endelse q=q;endmodule6.6.5module mealy_sequence_detector(a,cp,cr,y); input a,cp,cr; output y; reg y; reg1:0current_state,next_state; parameter s0=2b00, s1=2b01, s2=2b11;al

12、ways (negedge cp or negedgecr)begin if(cr) current_state=s0; else current_state= next_state;endalways (current_state or a)begin case(current_state)s0:begin y=0; next_state=(a=1)?s1:s0;ends1:begin y=0; next_state=(a=1)?s2:s0;ends2:if(a=1) begin y=0;next_state=s2;end else beginy=1; next_state=s0;endde

13、fult:begin y=0; next_state=s0;end endcaseendendmodule 6.6.6module moore_mdl(data,q,cp,cr); input data,cp,cr;output1:0 q;reg1:0 state;parameter s0=2b00, s1=2b01, s2=2b10,s3=2b11;always (posedge cp or negedge cr)begin if(cr) state=s0; elsecase(state) s0:if(data)state=s1; s1:if(data)state=s2;else state

14、=s3; s2:if(data)state=s3; s3:if(data)state=s0;endcaseendassign q=state;endmodule 7.5.1module basketball24(timerh,timerl,alarm,nrst,npause,cp); input nrst,npause,cp; wire nrst,npause,cp; output3:0 timerh,timerl;reg 3:0 timerh,timerl; output alarm;assign alarm=( timerh,timerl=8h00)&( nrst=1b1);always

15、(posedge cp or negedge nrst or negedge npause) begin if(nrst) timerh,timerl=8h24; else if (npause) timerh,timerl= timerh,timerl; else if ( timerh,timerl=8h00) begin timerh,timerl= timerh,timerl;end else if (timerl=4h0) begin timerh= timerh-1b1; timerl=4h9;end else begin timerh= timerh; timerl= timer

16、l-1b1;endendendmodule 7.5.2module top_clock (hour,minute,second,cp,ncr,en,adj_min,adj_hour); input cp,ncr,en,adj_min,adj_hour; output 7:0 hour,minute,second;wire 7:0 hour,minute,second;supplyl vdd;wire minl_en,minh_en,hour_en;counter10 u1(second3:0, ncr,en,cp); counter6 u2(second7:4, ncr,( second3:0

17、=4h9),cp); assign minl_en=adj_min?vdd:(second=8h59); assign minh_en=(adj_min&(minute3:0=4h9)| (minute3:0=4h9)&(second=8h59);counter10 u3 (minute3:0,ncr,minl_en,cp);counter6 u4 (minute7:4,ncr,minh_en,cp);assign hour_en=adj_hour?vdd:(minute=8h59)&(second=8h59);counter24 u5 (hour7:4,hour3:0,ncr,hour _e

18、n,cp);endmodule module counter10 (q, ncr,en,cp); input cp, ncr,en; output 3:0q; reg 3:0q;always (posedge cp or negedge ncr) begin if(ncr) q=4b0000; else if(en) q=q;else if(q=4b1001) q=4b0000;else q=q+1b1; endendmodule module counter6 (q, ncr,en,cp); input cp, ncr,en; output 3:0q; reg 3:0q;always (posedge cp or negedge ncr) begin if(ncr) q=4b0000; else if(en) q=q;else if(q=4b0101) q=4b0000;else q=q+1b1; endendmodule module counter24 (cnth,cntl, ncr,en,cp); input cp, ncr,en; output 3:0 cnth,cntl; reg 3:0 cnth,cntl; reg c