2011数字电路设计期末考试题-参考解答

1、学院姓名学号任课老师考场教室选课号/座位号密封线以内答题无效第6页共6页电子科技大学2010 -2011学年第学期期末考试A卷课程名称：数字逻辑设计及应用考试形式：闭卷 考试日期：20 11年7月 7 日考试时长：120分钟课程成绩构成：平时30%，期中 30%, 实验 0%，期末 40%本试卷试题由六部分构成，共_6页。4 bit binary nu mbers, that is, in clude 16 states at most.5 D filp-flops at least. A modulo-288 counter circuit needs 3题号-一-二二三四五、六七八九十合计

2、得分I. Fill your answers in the blanks (2 X0=20)1. A parity circuit with N inputs needN-1 XOR gates. If the number ofinain N logic variables set, such as A、B、C、W , is even number, thenABc”和=2. A circuit with 4 flip-flops can store3. A modulo-20 coun ter circuit n eeds4-bit coun ters of 74x163 at least

3、.4. A 8-bit ring coun ter has 8 no rmal states. If we want to realize the same nu mber no rmal states, we n eed a 4 bit twisted-ri ng coun ter.5. If the input is 10000000 of an 8 bit DAC, the corres ponding out put is 5v. Then an input is 00000001 to the DAC, the corres ponding out put is 5/128 (0.0

4、391) V; if an inp ut is 10001000, the corres ponding DAC out put is 5.3125 V.II. Please select the only one correct answer in the following questions.(X=10)1. We n eed (B ) chips of 4K 4 bits RAM to form a 16 K 8 bits RAM.A) 2B) 8C) 4D) 162. To design a 01101100 serial sequencegenerator by shift reg

5、isters, we need a ( A )-bit shift register as least.A) 5B) 4C) 3D) 63. For the follow ing latches or flip-flops,()can be used to form shift register.A) S-R latch B) master-slave fli p-flopC) S-R latch with en able D) S -R latch4. Which of the followi ng stateme nts is correct?(A) The out puts of a M

6、oore mach ine depend on inputs as well as the states.B) The out puts of a Mealy machi ne depend only on the states.C) The out puts of a Mealy machi ne depenobn inputs as well as the states.D) A), B), C) are wrong.5. There is a state/out put table of a seque ntial mach ine as the table 1, what the in

7、put seque ncejs detected?A) 11110B) 11010C)10010D)10110Table 1SX01AA,0B,0BC,0B,0CA,0D,0DC,0E,0EC,1B,0S*,ZIII.An alyze the seque ntial-circuit as show n in figure 1.15 1. Write out the excitati on equati ons, tran siti on equati ons and out put equati on. 5 2. Assume the initial state is Q 2Q1=00, co

8、mpiete the timing diagram for Q 2 ,Q1 and Z.( Don need consider propagation delay of each component) 10 0Q1I解答：Q1 = D1=Q1 Q2, Q2 =D2= Q/1+ Q/2Z= Q1?Q激励方程：D1=Q1 Q2，D2= Q/1+ q! 转移方程：输出方程：IV. Desig n a Mealy seque ntial detector with one input x and one out put z. If and only if xcontinues to be 1111 o

9、r 1001, the out put z is 1. Otherwise, the out put z is 0. The overla p is p ermitted. Pleasedescribe the state meaning and finish the state/out put table. 15Example：x： 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1z： 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1State mea ningIn itialAA,0B,0Received1BC,0D,0Received10CE,

10、0B,0Received11DC,0F,0Received100EA,0B,1Received111FC,0F,1S*,ZV. An alyze the circuit as show n below, which contains a 74x163 4-bit binary coun ter, a 74x138 decoder and a 74x153 4-i np ut,1-bit mult ip lexer. When control input MN=10 for 74x153 mult ip lexer,15 1. Write out the logic exp ression of

11、 74x153 out put F. 5 2. Write out the seque nee of states for the 74x161 in the circuit. 73. Describe the modulus（模）of the circuit. 3 74X161的功能表输入当前状态下一状态输出CLR LLD LENTENPQD QC QB QAQD* QC* QB* QA*RCO0XXXX X X X0 0 0 0010XXX X X XD C B A0110XX X X XQD QC QB QA011X0X X X XQD QC QB QA011110 0 0 00 0 0

12、 1011110 0 0 10 0 10011110 0 100 0 11011110 0 110 10 0011110111111110 0 0 01+5VCLK解答：F=D2=Y6/=(QDQCQBQA /)/状态序列：0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,0,1,2 M=15VI. Design a minimal-cost modulo-5 synchronous counter with D flip-flops and necessary gates,the state tran sition seque nee is 0 2 4 13 0 with the bin ary code. 15 1. Fill out the tran sitio n/out put table. 8 2. Write out the excitati on equati ons and out put equati on. 43. List the comp lete tran siti