计算机组成原理综合设计报告

1、华南农业大学信息学院设计性、综合性实验实验项目名称： 计算机组成原理综合设计实验项目性质： 综合性、设计性实验所属课程名称： 计算机组成原理开 设 时 间： 2009学年第一学期一、实验目的通过对简单微指令控制器的设计与实现，使抽象的理论原理在实践中得到应用，由此巩固学习内容。二、实验内容按照实验原理图设计并实现一个微型指令控制器，主要实现地址转换，指令储存等功能。三、 详细设计本微指令控制器由微指令寄存器和地址转移逻辑等几个部件组成，控制存储器用来存放实现全部指令系统的微程序；微指令寄存器用来存放由控制存储器读出的一条微指令信息，其中微地址寄存器决定将要访问的下一条微指令的地址，而微命令寄存

2、器则保存一条微指令的操作控制字段和判别测试字段的信息。最后地址转移逻辑用于根据从微指令中读出的P字段来判断下一条微指令的地址，承担自动完成修改微地址的任务。分别使用寄存器，控制存储器，逻辑转移指令，节拍发生器等部件实现。逻辑转移部件地址寄存器控制存储器P字段OP/地址寄存器library ieee;use ieee.std_logic_1164.all;entity addr_logic isport(p_segment,op : in std_logic_vector(1 downto 0); get_op,clk : in std_logic; addr_out : out std_log

3、ic_vector(1 downto 0);end addr_logic;architecture addrlogic of addr_logic isbegin process(p_segment,op,get_op,clk) begin if rising_edge(clk) thenif get_op=1 thenaddr_out=op;end if;end if; end process;end addrlogic;/计时器library ieee;use ieee.std_logic_1164.all;entity pulse isport(clk,clr : in std_logi

4、c; t : out std_logic_vector(4 downto 1);end pulse;architecture s_pulse of pulse iscomponent wdff isport(d,clk,r,s : in std_logic; q,nq : out std_logic);end component;signal c,nc : std_logic_vector(4 downto 1);signal cp,nclk,rr : std_logic;begin nclk=not clk; c4 : wdff port map(c(3),nclk,1,clr,c(4),n

5、c(4); cp=not (nclk and nc(4); rr=not (clk and c(4); c1 : wdff port map(1,cp,rr,1,c(1),nc(1); c2 : wdff port map(c(1),cp,rr,1,c(2),nc(2); c3 : wdff port map(c(2),cp,rr,1,c(3),nc(3); t(1)=c(1) and nc(2); t(2)=c(2) and nc(3); t(3)=c(3);t(4)=nc(1);end s_pulse;/总控制器library ieee; use ieee.std_logic_1164.a

6、ll;entity add isport(addin : in std_logic_vector(3 downto 0); clk : in std_logic; addout : out std_logic_vector(3 downto 0);end add;architecture s_add of add iscomponent wdff isport(d,clk,r,s : in std_logic; q,nq : out std_logic);end component;begin w1: wdff port map(addin0,clk,1,1,addout0,0); w2: w

7、dff port map(addin1,clk,1,1,addout1,0); w3: wdff port map(addin2,clk,1,1,addout2,0); w4: wdff port map(addin3,clk,1,1,addout3,0);end s_add;signal c1,c2,c3,c4 : std_logic_vector(4 downto 2);signal y1,y2,y3,y4 : std_logic_vector(4 downto 1);signal s1,s2,s3 : std_logic_vector(4 downto 1);/控制存储器library

8、ieee;use ieee.std_logic_1164.all;entity rom isport(addr : in std_logic_vector(1 downto 0); ce : in std_logic; dataout : out std_logic_vector(22 downto 0);end rom;architecture b_rom of rom isbegin dataout=1 when addr=00 and ce=1 else 0 when addr=01 and ce=1 else 0 when addr=10 and ce=1 else 0;end b_r

9、om;/逻辑转换器library ieee; use ieee.std_logic_1164.all;entity logic_change isport( op : in std_logic_vector(3 downto 0); p : in std_logic_vector(5 downto 0); clk: in std_logic; c: in std_logic; addout : out std_logic_vector(3 downto 0); end logic_change;architecture s_logic_change of logic_chang isbegin

10、 process(op,next,p,clk,addout) begin addout13=p5 and p0 and p1; addout12=p4 and p0 and p1; addout11=p3 and p0 and p1; addout10=p2 and p0 and p1; addout23=p5 and p0; addout22=0; addout21=p3 and p0; addout20=0; addout33=p5 or 0; addout32=p4 or 0; addout31=p3 or 0; addout30=p2 and p1; addout=(addout1 a

11、nd (not p1) and (not p0) or (addout2 and p0) or (addout3 and p1); end process;end s_logic_change;/主模块LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;use ieee.numeric_std.all;ENTITY test IS PORT( op : IN STD_LOGIC_VECTOR(1 DOWNTO 0);ra,rb : in std_logic_vector(4 downto 0);get_o

12、p,clk,clr : in std_logic; data_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 1) );END test;architecture my_test of test iscomponent rom isport(addr : in std_logic_vector(1 downto 0); ce : in std_logic; dataout : out std_logic_vector(22 downto 0);end component;component pulse isport(clk,clr : in std_logic; t :

13、 out std_logic_vector(4 downto 1);end component;component maddr_r isport(clk,clr : in std_logic;maddr_in : in std_logic_vector(2 downto 1); maddr_out : out std_logic_vector(2 downto 1);end component;component mcmd_r isport(clk,clr : in std_logic;mcmd_in : in std_logic_vector(23 downto 1); mcmd_out :

14、 out std_logic_vector(23 downto 1);end component;component addr_logic isport(p_segment,op : in std_logic_vector(1 downto 0); get_op,clk : in std_logic; addr_out : out std_logic_vector(1 downto 0);end component;component add_sub isport(a,b : in std_logic_vector(5 downto 1);cs,ci : in std_logic; s : o

15、ut std_logic_vector(5 downto 1) );end component;component bcd isPORT( a : in STD_LOGIC_VECTOR(4 DOWNTO 0); b : in STD_LOGIC_VECTOR(4 DOWNTO 0); cs : in std_logic; c : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );end component;signal t : std_logic_vector(3 downto 0); -脉冲信号；signal p_seg : std_logic_vector(1 dow

16、nto 0); -p字段；signal addr_o1,addr_o2 : std_logic_vector(1 downto 0); -逻辑转移部件输出；signal d_out,control : std_logic_vector(22 downto 0);signal temp_out,temp_out2 : std_logic_vector(4 downto 0);beging1:pulse port map(clk,clr,t);g2:addr_logic port map(p_seg,op,get_op,t(0),addr_o1);g3:maddr_r port map(t(1),

17、clr,addr_o1,addr_o2);g4:rom port map(addr_o2,t(2),d_out);g5:mcmd_r port map(t(3),clr,d_out,control);g6:add_sub port map(ra,rb,control(22),control(21),temp_out);g7:bcd port map(ra,rb,control(20),temp_out2);process(control,temp_out,temp_out2)beginif control(22)=1 thendata_out=temp_out;elsif control(20

18、)=1 thendata_out=temp_out2;end if;end process;end my_test;/ /控制存储器port(d,clk,r,s : in std_logic; q,nq : out std_logic);end wdff;library ieee;use ieee.std_logic_1164.all;entity wdff isport(d,clk,r,s : in std_logic; q,nq : out std_logic);end wdff;architecture b_wdff of wdff isbegin process(d,clk,r,s)

19、begin if r=0 then q=0; nq=1; elsif s=0 then q=1; nq=0; elsif rising_edge(clk) then q=d; nq=not d; end if; end process;end b_wdff;library ieee;use ieee.std_logic_1164.all;entity mcmd_r isport(clk,clr : in std_logic;mcmd_in : in std_logic_vector(23 downto 1); mcmd_out : out std_logic_vector(23 downto

20、1);end mcmd_r;architecture mcmd of mcmd_r iscomponent wdff isport(d,clk,r,s : in std_logic; q,nq : out std_logic);end component;signal c,nc : std_logic_vector(23 downto 1);signal nclk : std_logic;begin nclk=not clk; c1 : wdff port map(mcmd_in(1),clk,clr,1,c(1),nc(1); c2 : wdff port map(mcmd_in(2),cl

21、k,clr,1,c(2),nc(2); c3 : wdff port map(mcmd_in(3),clk,clr,1,c(3),nc(3); c4 : wdff port map(mcmd_in(4),clk,clr,1,c(4),nc(4); c5 : wdff port map(mcmd_in(5),clk,clr,1,c(5),nc(5); c6 : wdff port map(mcmd_in(6),clk,clr,1,c(6),nc(6); c7 : wdff port map(mcmd_in(7),clk,clr,1,c(7),nc(7); c8 : wdff port map(m

22、cmd_in(8),clk,clr,1,c(8),nc(8); c9 : wdff port map(mcmd_in(9),clk,clr,1,c(9),nc(9); c10 : wdff port map(mcmd_in(10),clk,clr,1,c(10),nc(10); c11 : wdff port map(mcmd_in(11),clk,clr,1,c(11),nc(11); c12 : wdff port map(mcmd_in(12),clk,clr,1,c(12),nc(12); c13 : wdff port map(mcmd_in(13),clk,clr,1,c(13),

23、nc(13); c14 : wdff port map(mcmd_in(14),clk,clr,1,c(14),nc(14); c15 : wdff port map(mcmd_in(15),clk,clr,1,c(15),nc(15); c16 : wdff port map(mcmd_in(16),clk,clr,1,c(16),nc(16); c17 : wdff port map(mcmd_in(17),clk,clr,1,c(17),nc(17); c18 : wdff port map(mcmd_in(18),clk,clr,1,c(18),nc(18); c19 : wdff port map(mcmd_in(19),clk,clr,1,c(19),nc(19);