文献翻译——什么是ARM Cortex-M3处理器？

苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第1页外文文献资料收集：苏州大学应用技术学院11电子（1116405006）姚瑞东WhatistheARMCortex-M3processor?Themicrocontrollermarketisvast,withover20billiondevicesperyearestimatedtobeshippedin2010.Abewilderingarrayofvendors,devices,andarchitecturesarecompetinginthismarket.Therequirementforhigher-performancemicrocontrollershasbeendrivengloballybytheindustryschangingneeds;forexample,microcontrollersarerequiredtohandlemoreworkwithoutincreasingaproductsfrequencyorpower.Inaddition,microcontrollersarebecomingincreasinglyconnected,whetherbyUniversalSerialBus(USB),Ethernet,orWirelessRadio,andhencetheprocessingneededtosupportthesecommunicationschannelsandadvancedperipheralsisgrowing.Similarly,generalapplicationcomplexityisontheincrease,drivenbymoresophisticateduserinterfaces,multimediarequirements,systemspeed，andconvergenceoffunctionalities.TheARMCortex-M3processor,thefirstoftheCortexgenerationofprocessorsreleasedbyARMin2006，wasprimarilydesignedtotargetthe32-bitmicrocontrollermarket.TheCortex-M3processorprovidesexcellentperformanceatlowgatecountandcomeswithmanynewfeaturespreviouslyavailableonlyinhigh-endprocessors.TheCortex-M3addressesthenewfeaturespreviouslyavailableonlyinhigh-endprocessors.TheCortex-M3addressestherequirementsforthe32-bitembeddedprocessormarketinthefollowingways:Greaterperformanceefficiency，allowingmoreworktobedonewithoutincreasingthefrequencyorpowerrequirements.Lowpowerconsumption,enablinglongerbatterylife,especiallycriticalinportableproductsincludingwirelessnetworkingapplications.Enhanceddeterminism,guaranteeingthatcriticaltasksandinterruptsareservicedasquicklyaspossiblebutinaknownnumberofcycles.Improvedcodedensity,ensuringthatcodefitsineventhesmallestmemoryfootprints.Easeofuse,providingeasierprogrammabilityanddebuggingforthegrowingnumberof8-bitand16-bitusersmigratingto32-bit.Lower-costsolutions,reducing32-bit-basedsystemcostsclosetothoseoflegacy8-bitand16-bitdevicesandenablinglow-end,32-bitmicrocontrollerstobepricedatlessthanUS$1forthefirsttime.Widechoiceofdevelopmenttools,fromlow-costorfreecompilerstofull-featureddevelopmentsuites苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第2页frommanydevelopmenttoolvendors.MicrocontrollersbasedontheCortex-M3processoralreadycompetehead-onwithdevicesbasedonawidevarietyofotherarchitectures.Designersareincreasinglylookingatreducingthesystemcost,asopposedtothetraditionaldevicecost.Assuch,organizationsareimplementingdeviceaggregation,wherebyasingle,morepowerfuldevicecanpotentiallyreplacethreeorfourtraditional8-bitdevices.Othercostsavingscanbeachievedbyimprovingtheamountofcodereuseacrossallsystems.SinceCortex-M3processor-basedmicrocontrollerscanbeeasilyprogrammedusingtheClanguageandarebasedonawell-establishedarchitecture,applicationcodecanbeportedandreusedeasily,reducingdevelopmenttimeandtestingcosts.ItisworthwhilehighlightingthattheCortex-M3processorisnotthefirstARMprocessortobeusedtocreategenericmicrocontrollers.ThevenerableARM7processorhasbeenverysuccessfulinthismarket,withpartnerssuchasNXP(Philips),TexasInstruments,Atmel，OKI,andmanyothervendorsdeliveringrobust32-bitMicrocontrollerUnits(MCU).TheARM7isthemostwidelyused32-bitembeddedprocessorinhistory,withover1billionprocessorsproducedeachyearinahugevarietyofelectronicproducts,frommobilephonestocars.TheCortex-M3processorivscortex-M3-BasedMCUTheCortex-M3processoristhecentralprocessingunit(CPU)ofamicrocontrollerchip.Inaddition,anumberofothercomponentsarerequiredforthewholeCortex-M3processor-basedmicrocontroller.AfterchipmanufacturerslicensetheCortex-M3processor,theycanputtheCortex-M3processorintheirsilicondesigns,addingmemory,peripherals,input/output(I/O),andotherfeatures.Cortex-M3processor-basedchipsfromdifferentmanufacturerswillhavedifferentmemorysizes,types,peripherals,andfeatures.Thisbookfocusesonthearchitectureoftheprocessorcore.Fordetailsabouttherestofthechip，pleasechecktheparticularchipmanufacturersdocumentation.Figure1Cortex-M3苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第3页BackgroundofARMandARMArchitectureABriefHistoryTohelpyouunderstandthevariationsofARMprocessorsandarchitectureversions,letslookatalittlebitofARMhistory.ARMwasformedin1990asAdvancedRISCMachinesLtd.,ajointventureofAppleComputer,AcornComputerGroup,andVLSITechnology.In1991，ARMintroducedtheARM6processorfamily,andVLSIbecametheinitiallicensee.Subsequently,additionalcompanies,includingTexasInstruments,NEC,Sharp,andSTMicroelectronics,licensedtheARMprocessordesigns,extendingtheapplicationsofARMprocessorsintomobilephones,computerharddisks,personaldigitalassistants(PDASs),homeentertainmentsystems，andmanyotherconsumerproducts.NowadaysARMpartnersshipinexcessof2billionARMprocessorseachyear.Unlikemanysemiconductorcompanies,ARMdoesnotmanufactureprocessorsorsellthechipsdirectly.Instead,ARMlicensestheprocessordesignstobusinesspartners,includingamajorityoftheworldsleadingsemiconductorcompanies.BasedontheARMlow-costandpower-efficientprocessordesigns，thesepartnerscreatetheirprocessors,microcontrollers,andsystem-on-chipsolutions.Thisbusinessmodeliscommonlycalledintellectualproperty(IP)licensing.Inadditiontoprocessordesigns，ARMalsolicensessystems-levelIPandvarioussoftwareIP.Tosupporttheseproducts,ARMhasdevelopedastrongbaseofdevelopmenttools,hardware,andsoftwareproductstoenablepartnerstodeveloptheirownproducts.ArchitectureVersionsOvertheyears,ARMhascontinuedtodevelopnewprocessorsandsystemblocks.TheseincludethepopularARM7TDMIprocessorand,morerecently,theARM1176TZ(F)-Sprocessor,whichisusedinhigh-endapplicationssuchassmartphones.TheevolutionoffeaturesandenhancementstotheprocessorsovertimehasledtosuccessiveversionsoftheARMarchitecture.Notethatarchitectureversionnumbersareindependentfromprocessornames.Forexample，theARM7TDMIprocessorisbasedontheARMv4Tarchitecture(theTisforThumbinstructionmodesupport).TheARMv5EarchitecturewasintroducedwiththeARM9Eprocessorfamilies,includingtheARM926E-SandARM946E-Sprocessors.Thisarchitectureadded“Enhanced”DigitalSignalProcessing(DSP)instructionsformultimediaapplications.WiththearrivaloftheARM11processorfamily,thearchitecturewasextendedtotheARMv6.NewfeaturesinthisarchitectureincludedmemorysystemfeaturesandSingleInstruction-MultipleData(SIMD)instructions.ProcessorsbasedontheARMv6architectureincludetheARM1136J(F)-S,theARM1156T2(F)-苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第4页S,andtheARM1176JZ(F)-S.FollowingtheintroductionoftheARM11family,itwasdecidedthatmanyofthenewtechnologies,suchastheoptimizedThumb-2instructionset,werejustasapplicabletothelower-costmarketsofmicrocontrollerandautomotivecomponents.ItwasalsodecidedthatalthoughthearchitectureneededtobeconsistentfromthelowestMCUtothehighest-performanceapplicationprocessor,therewasaneedtodeliverprocessorarchitecturesthatbestfitapplications,enablingverydeterministicandlowgatecountprocessorsforcost-sensitivemarketsandfeature-richandhigh-performanceonesforhigh-endapplications.Overthepastseveralyears,ARMextendeditsproductportfoliobydiversifyingitsCPUdevelopment,whichresultedinthearchitectureversion7，orv7.Inthisversion,thearchitecturedesignisdividedintothreeprofiles:TheAprofile,designedforhigh-performanceopenapplicationplatformsTheRprofile,designedforhigh-endembeddedsystemsinwhichreal-timeperformanceisneededTheMprofile,designedfordeeplyembeddedmicrocontroller-typesystemsLetslookattheseprofilesinabitmoredetail:AProfile(ARMv7-A):Applicationprocessorsrequiredtoruncomplexapplicationssuchashigh-endembeddedoperatingsystems(OS),suchasSym,Linux,andWindowsEmbedded,requiringthehighestprocessingpower,virtualmemorysystemsupportwithMemoryManagementUnits(MMU),and,optionally,enhancedJavasupportandasecureprogramexecutionenvironment.Exampleproductsincludehigh-endmobilephonesandelectronicwalletsforfinancialtransactions.RProfile(ARMv7-R):Real-time,high-performanceprocessorstargetedprimarilyatthehigherendofthereal-time1market-thoseapplications,suchashigh-endbreakingsystemsandharddrivecontrollers,inwhichhighprocessingpowerandhighreliabilityareessentialandforwhichlowlatencyisimportant.MProfile(ARMv7-M):Processorstargetinglow-costapplicationsinwhichprocessingefficiencyisimportantandcost,powerconsumption,lowinterruptlatency,andeaseofusearecritical，aswellasindustrialcontrolapplications,includingreal-timecontrolTheCortexprocessorfamiliesarethefirstproductsdevelopedonarchitecturev7,andtheCortex-M3processorisbasedononeprofileofthev7architecture,calledARMv7-M,anarchitecturespecificationformicrocontrollerproducts.ThisbookfocusesontheCortex-M3processor,butitisonlyoneoftheCortexproductfamilythatusestheARMv7architecture.OtherCortexfamilyprocessorsincludetheCortex-A8(applicationprocessor),whichisbasedontheARMv7-Aprofile,andtheCortex-R4(real-timeprocessor),basedontheARMv7-Rprofile.苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第5页Figure1.2TheEvolutionofARMProcessorArchitectureThedetailsoftheARMv7-MarchitecturearedocumentedinTheARMv7-MArchitectureApplicationLevelReferenceManual(Ref2).ThisdocumentcanbeobtainedviatheARMWebsitethroughasimpleregistrationprocess.TheARMv7-Marchitecturecontainsthefollowingkeyareas:ProgrammersmodelInstructionsetMemorymodelDebugarchitectureProcessor-specificinformation,suchasinterfacedetailsandtiming,isdocumentedintheCortex-M3TechnicalReferenceManual(TRM)(Ref1).ThismanualcanbeaccessedfreelyontheARMWebsite.TheCortex-M3TRMalsocoversanumberofimplementationdetailsnotcoveredbythearchitecturespecifications,suchasthelistofsupportedinstructions,becausesomeoftheinstructionscoveredintheARMv7-MarchitecturespecificationareoptionalonARMv7-Mdevices.ProcessorNamingTraditionally,ARMusedanumberingschemetonameprocessors.Intheearlydays(the1990s),suffixeswerealsousedtoindicatefeaturesontheprocessors.Forexample,withtheARM7TDMIprocessor,theTindicatesThumbinstructionsupport,DindicatesJTAGdebugging,Mindicatesfastmultiplier,andIindicatesanembeddedICEmodule.SubsequentlyitwasdecidedthatthesefeaturesshouldbecomestandardfeaturesoffutureARMprocessors;therefore,thesesuffixesarenolongeraddedtothenewprocessorfamilynames.Instead,variationsonmemoryinterface,cache,andTightlyCoupledMemory(TCM)havecreatedanewschemeforprocessornaming.Forexample,ARMprocessorswithcacheandMMUarenowgiventhesuffix“26”or“36，”whereasprocessorswithMemoryProtectionUnits(MPU)aregiventhesuffix“46”（e.g.，ARM946E-S).Inaddition，othersuffixesareaddedtoindicatesynthesizable2(S)andJazelleJAZELLE(J)technology.Table1.1presentsasummaryofprocessornames.苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第6页Withversion7ofthearchitecture,ARMhasmigratedawayfromthesecomplexnumberingschemesthatneededtobedecoded,movingtoaconsistentnamingforfamiliesofprocessors,withCortexitsinitialbrand.Inadditiontoillustratingthecompatibilityacrossprocessors,thissystemremovesconfusionbetweenarchitecturalversionandprocessorfamilynumber;forexample,theARM7TDMIisnotav7processorbutwasbasedonthev4Tarchitecture.InstructionSetDevelopmentEnhancementandextensionofinstructionsetsusedbytheARMprocessorshasbeenoneofthekeydrivingforcesofthearchitecturesevolution.Historically(sinceARM7TDMI),twodifferentinstructionsetsaresupportedontheARMprocessor:theARMinstructionsthatare32-bitandThumbinstructionsthatare16-bit.Duringprogramexecution,theprocessorcanbedynamicallyswitchedbetweentheARMstateortheThumbstatetouseeitheroneoftheinstructionsets.TheThumbinstructionsetprovidesonlyasubsetoftheARMinstructions,butitcanprovidehighercodedensity.Itisusefulforproductswithtightmemoryrequirements.Asthearchitectureversionhasbeenupdated,extrainstructionshavebeenaddedtobothARMinstructionsandtheThumbinstructions.AppendixIIprovidessomeinformationonthechangeofThumbinstructionsduringthearchitectureenhancements.In2003，ARMannouncedtheThumb-2instructionset,whichisanewsupersetofThumbinstructionsthatcontainsboth16-bitand32-bitinstructions.ThedetailsoftheinstructionsetareprovidedinadocumentcalledTheARMArchitectureReferenceManual(alsoknownastheARM).ThismanualhasbeenupdatedfortheARMv5architecture,theARMv6architecture,andtheARMv7architecture.FortheARMv7architecture,duetoitsgrowthintodifferentprofiles,thespecificationisalsosplitintodifferentdocuments.ForCortex-M3developers,theARMv7-MArchitectureApplicationLevelReferenceManual(Ref2)coversalltherequiredinstructionsetdetails.TheThumb-2InstructionSetArchitecture(ISA)TheThumb-23ISAisahighlyefficientandpowerfulinstructionsetthatdeliverssignificantbenefitsintermsofeaseofuse,codesize,andperformance.TheThumb-2instructionsetisasupersetoftheprevious16-bitThumbinstructionset,withadditional16-bitinstructionsalongside32-bitinstructions.ItallowsmorecomplexoperationstobecarriedoutintheThumbstate,thusallowinghigherefficiencybyreducingthenumberofstatesswitchingbetweenARM苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第7页Figure1.43TherelationshipBetweentheThumb-2InstructionSetandtheThumbInstructionSetFocusedonsmallmemorysystemdevicessuchasmicrocontrollersandreducingthesizeoftheprocessor,theCortex-M3supportsonlytheThumb-2(andtraditionalThumb)instructionset.InsteadofusingARMinstructionsforsomeoperations,asintraditionalARMprocessors,itusestheThumb-2instructionsetforalloperations.Asaresult,theCortex-M3processorisnotbackwardcompatiblewithtraditionalARMprocessors.Thatis,youcannotrunabinaryimageforARM7processorsontheCortex-M3processor.Nevertheless,theCortex-M3processorcanexecutealmostallthe16-bitThumbinstructions,includingall16-bitThumbinstructionssupportedonARM7familyprocessors,makingapplicationportingeasy.Withsupportforboth16-bitand32-bitinstructionsintheThumb-2instructionsset,thereisnoneedtoswitchtheprocessorbetweenThumbstate(16-bitinstructions)andARMstate(32-bitinstructions).Forexample,inARM7orARM9familyprocessors,youmightneedtoswitchtoARMstateifyouwanttocarryoutcomplexcalculationsoralargenumberofconditionaloperationsandgoodperformanceisneeded;whereasintheCortex-M3processoryoucanmix32-bitinstructionswith16-bitinstructionswithoutswitchingstate,gettinghighcodedensityandhighperformancewithnoextracomplexity.TheThumb-2instructionsetisaveryimportantfeatureoftheARMv7architecture.ComparedwiththeinstructionssupportedonARM7familyprocessors(ARMv4Tarchitecture),theCortex-M3processorinstructionsethasalargenumberofnewfeatures.Forthefirsttime,hardwaredivideinstructionisavailableonanARMprocessor,andanumberofmultiplyinstructionsarealsoavailableontheCortex-M3processortoimprovedata-crunchingperformance.TheCortex-M3processoralsosupportsunaligneddataaccesses,afeaturepreviouslyavailableonlyinhigh-endprocessors.Cortex-M3ProcessorApplicationsWithitshighperformanceandhighcodedensityandsmallsiliconfootprinttheCortex-M3processorisidealforawidevarietyofapplications:苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第8页Low-costmicrocontrollers:TheCortex-M3processorisideallysuitedforlow-costmicrocontrollers,whicharecommonlyusedinconsumerproducts,fromtoystoelectricalappliances.Itisahighlycompetitivemarketduetothemanywell-known8-bitand16-bitmicrocontrollerproductsonthemarket.Itslowerpower,highperformance,andease-of-useadvantagesenableembeddeddeveloperstomigrateto32-bitsystemsanddevelopproductswiththeARMarchitecture.Automotive:AnotheridealapplicationfortheCortex-M3processorisintheautomotiveindustry.TheCortex-M3processorhasveryhigh-performanceefficiencyandlowinterruptlatency,allowingittobeusedinreal-timesystems.TheCortex-M3processorsupportsupto240externalvectoredinterrupts,withabuilt-ininterruptcontrollerwithnestedinterruptsupportsandanoptionalmemoryprotectionunit,makingitidealforhighlyintegratedandcost-sensitiveautomotiveapplications.Datacommunications:Theprocessorslowpowerandhighefficiency,coupledwithThumb-2instructionsforbit-fieldmanipulation,maketheCortex-M3idealformanycommunicationsapplications,suchasBluetoothandZigBeeZIGBEE.Industrialcontrol:Inindustrialcontrolapplications,simplicity,fastresponse,andreliabilityarekeyfactors.Again，theCortex-M3processorsinterruptfeature，lowinterruptlatency,andenhancedfault-handlingfeaturesmakeitastrongcandidateinthisarea.Consumerproducts:Inmanyconsumerproducts,ahigh-performancemicroprocessor(orseveralofthem)isused.TheCortex-M3processor,beingasmallprocessor,ishighlyefficientandlowinpowerandsupportsanMPUenablingcomplexsoftwaretoexecutewhileprovidingrobustmemoryprotection.TherearealreadymanyCortex-M3processor-basedproductsavailableinthemarket,includinglow-endproductspricedaslowasUS$1,makingthecostofARMmicrocontrollerscomparabletoorlowerthanthatofmany8-bitmicrocontrollers.OrganizationofThisBookThisbookcontainsageneraloverviewoftheCortex-M3processor,withtherestofthecontentsdividedintoanumberofsections:Chapters1and2，IntroductionandOverviewoftheCortex-M3Chapters3-6,Cortex-M3BasicsChapters7-9，ExceptionsandInterruptsChapters10and11,Cortex-M3ProgrammingChapters12-14,Cortex-M3HardwareFeaturesChapters15and16，DebugSupportsinCortex-M3Chapters17-20,ApplicationDevelopmentwithCortex-M3苏州大学本科生毕业设计（论文）附件：外文文献资料与中文翻译稿第9页FurtherReadingsThisbookdoesnotcontainallthetechnicaldetailsontheCortex-M3processor.ItisintendedtobeastarterguideforpeoplewhoarenewtotheCortex-M3processorandasupplementalreferenceforpeopleusingCortex-M3processor-basedmicrocontrollers.TogetfurtherdetailontheCortex-M3processor,thefollowingdocuments,availablefromARM()andARMpartnerWebsites,shouldcovermostnecessarydetails:TheCortex-M3TechnicalReferenceManual(TRM)(Ref1)providesdetailedinformationabouttheprocessor,includingprogrammersmodel,memorymap，andinstructiontiming.TheARMv7-MArchitectureApplicationLevelRefewnceManual(Ref2)containsdetailedinformationabouttheinstructionsetandthememorymodel.RefertodatasheetsfortheCortex-M3processor-basedmicrocontrollerproducts;visitthemanufacturerWebsiteforthedatasheetsontheCortex-M3processor-basedproductyouplantouse.RefertoAMBASpecification2.0(Ref4)formoredetailregardinginternalAMBAinterfacebusprotocoldetails.CprogrammingtipsforCortex-M3canbefoundintheARMApplicationNote179:Cortex-M3EmbeddedSoftwareDevelopment(Ref7).Thisbookassumesthatyoualreadyhavesomeknowledgeofandexperiencewithembeddedprogramming,preferablyusingARMprocessors.IfyouareamanagerorastudentwhowantstolearnthebasicswithoutspendingtoomuchtimereadingthewholebookortheTRM,Chapter2ofthisbookisagoodonetoread,sinceitprovidesasummaryontheCortex-M3processor.FundamentalsTheCortex-M3isa32-bitmicroprocessor.Ithasa32-bitdatapath,a32-bitregisterbank,and32-bitmemoryinterfaces.TheprocessorhasaHarvardarchitecture,whichm